Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
☆44May 29, 2025Updated 11 months ago
Alternatives and similar repositories for RTL-Timer
Users that are interested in RTL-Timer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 11 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 5 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆61Oct 28, 2024Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆18Dec 18, 2023Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆16Jan 29, 2024Updated 2 years ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆37Apr 13, 2025Updated last year
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 4 months ago
- ☆46May 18, 2024Updated last year
- An open-source benchmark for generating design RTL with natural language☆190Nov 8, 2024Updated last year
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25Dec 21, 2025Updated 4 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆289Feb 9, 2025Updated last year
- ☆20Oct 27, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆42Jul 17, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 4 months ago
- ☆17Apr 16, 2024Updated 2 years ago
- [DAC2024] Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration☆10Oct 31, 2024Updated last year
- Research paper based on or related to ABC.☆72Jan 19, 2026Updated 3 months ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆24May 24, 2025Updated 11 months ago
- ☆206Oct 17, 2024Updated last year
- ☆60Jan 19, 2026Updated 3 months ago
- ICCD'24 paper: "AutoVCoder: A systematic framework for automated verilog code generation"☆23Dec 17, 2024Updated last year
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 6 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆28Apr 9, 2025Updated last year
- ☆18Jul 12, 2024Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆42Apr 10, 2026Updated 3 weeks ago
- ☆25Jun 23, 2024Updated last year
- ☆19Jan 2, 2026Updated 4 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆59Jul 1, 2024Updated last year