hkust-zhiyao / RTL-TimerLinks
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
☆29Updated 3 weeks ago
Alternatives and similar repositories for RTL-Timer
Users that are interested in RTL-Timer are comparing it to the libraries listed below
Sorting:
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆31Updated 7 months ago
- ☆18Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- This is a python repo for flattening Verilog☆18Updated last month
- ☆25Updated last year
- ☆22Updated last year
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 5 months ago
- ☆31Updated last year
- This is a repo to store circuit design datasets☆18Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- ☆28Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 8 months ago
- Research paper based on or related to ABC.☆44Updated 3 weeks ago
- ☆16Updated 3 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆33Updated 11 months ago
- ☆16Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆49Updated 5 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆28Updated this week
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆17Updated 6 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆17Updated 2 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆22Updated last year
- Dataset for ML-guided Accelerator Design☆37Updated 7 months ago
- GPU-based logic synthesis tool☆81Updated 11 months ago
- ☆15Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated last month
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆19Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆19Updated 2 months ago