hkust-zhiyao / RTL-Timer
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
☆22Updated 8 months ago
Alternatives and similar repositories for RTL-Timer:
Users that are interested in RTL-Timer are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆42Updated 5 months ago
- This is a python repo for flattening Verilog☆16Updated 2 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆23Updated 4 months ago
- ☆28Updated 9 months ago
- ☆15Updated 2 years ago
- ☆22Updated 8 months ago
- This is a repo to store circuit design datasets☆15Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆46Updated 3 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 2 months ago
- ☆16Updated 3 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆15Updated 3 months ago
- Research paper based on or related to ABC.☆28Updated 2 weeks ago
- ☆25Updated 10 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆17Updated 5 months ago
- ☆16Updated 4 years ago
- GPU-based logic synthesis tool☆81Updated 7 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated this week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆43Updated 2 months ago
- ☆28Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆31Updated last month
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 6 months ago
- The open-sourced version of BOOM-Explorer☆37Updated last year
- ☆14Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆21Updated last year
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- ☆12Updated 2 years ago
- Dataset for ML-guided Accelerator Design☆35Updated 3 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆12Updated 2 years ago