Alternatives and similar repositories for AutoSVA2:

Users that are interested in AutoSVA2 are comparing it to the libraries listed below

• Entropy-xcy / sns
  ☆15Updated 2 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago
• sterin / super-prove-build
  ☆12Updated 4 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated last month
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆11Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆13Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆81Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆27Updated 6 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 4 months ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆22Updated last year
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆18Updated last month
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆33Updated 3 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆48Updated this week
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆47Updated 7 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆30Updated last year
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆55Updated this week
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆17Updated last year
• cure-lab / DeepGate2
  ☆15Updated last year
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆36Updated this week