Alternatives and similar repositories for owl

Users that are interested in owl are comparing it to the libraries listed below

• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• iscas-tis / CHA
  ☆19Updated last year
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 2 years ago
• mohdomama / Quine-McCluskey
  A Python/C++ implementation of Quine McCluskey(Tabulation) method.
  ☆12Updated 7 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated last week
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆15Updated last month
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• amahzoon / genmul
  ☆18Updated 4 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆36Updated last year
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• milo168 / FPGA25_SAT_Accel
  FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository
  ☆13Updated 6 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆32Updated last year
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 4 months ago
• Yu-Maryland / Differentiable_Scheduler_ICML24
  Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.
  ☆20Updated 11 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆12Updated 3 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 11 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆30Updated 6 months ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 4 years ago
• ckchengucsd / SMTCellUCSD
  Cell Layout Generation for DTCO/STCO Exploration Toolkit
  ☆21Updated 4 months ago
• euphoric-hardware / rtl-simulation-reading
  ☆17Updated 3 months ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 3 months ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• pku-liang / Hestia
  ☆17Updated 6 months ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year