UCSBarchlab / owlLinks
Control Logic Synthesis: Drawing the Rest of the OWL
☆13Updated last year
Alternatives and similar repositories for owl
Users that are interested in owl are comparing it to the libraries listed below
Sorting:
- ☆12Updated 2 years ago
- BTOR2 MLIR project☆26Updated last year
- Random Generator of Btor2 Files☆10Updated 2 years ago
- Arithmetic multiplier benchmarks☆11Updated 7 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 3 years ago
- FPGA synthesis tool powered by program synthesis☆51Updated 3 weeks ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Updated last month
- ☆19Updated last year
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- ☆18Updated 4 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆32Updated last year
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆20Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆36Updated last year
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆15Updated 3 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- ☆13Updated 4 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Updated 7 months ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Updated 3 months ago
- A Python/C++ implementation of Quine McCluskey(Tabulation) method.☆12Updated 7 years ago
- ☆17Updated 7 months ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆21Updated 5 months ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- MLIR+EqSat☆18Updated 2 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated this week
- ☆14Updated 7 years ago
- ☆24Updated 4 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- Integer Multiplier Generator for Verilog☆23Updated 3 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆30Updated 6 months ago