LLM Evaluation Benchmark on Hardware Formal Verification
☆44Apr 3, 2025Updated last year
Alternatives and similar repositories for FVEval
Users that are interested in FVEval are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆26Jun 9, 2025Updated last year
- ☆30Jan 30, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 8 months ago
- ☆28Aug 18, 2025Updated 11 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Jan 20, 2023Updated 3 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- ☆18Nov 19, 2023Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆64Oct 28, 2024Updated last year
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆16Aug 13, 2022Updated 3 years ago
- ☆15Dec 6, 2023Updated 2 years ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated last year
- ☆16May 2, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆29Apr 9, 2025Updated last year
- Verilog evaluation benchmark for large language model☆453Jul 14, 2025Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆33Mar 31, 2025Updated last year
- ☆194Jun 8, 2026Updated last month
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆22Jan 28, 2026Updated 5 months ago
- Generative Benchmark for LLM-Aided Hardware Design☆29Jun 4, 2025Updated last year
- A Lean-embedded framework to verify Verilog modules☆15Jul 3, 2026Updated 3 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- 面向 AI 编程 Agent 的开源形式验证技能库,聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV,…☆21Updated this week
- LLM-Assisted Hardware Formal Verification Tool☆111Jul 13, 2026Updated last week
- ☆49May 18, 2024Updated 2 years ago
- Equivalence checking with Yosys☆59Updated this week
- Fix syntax errors of LLM-generated RTL☆57May 23, 2024Updated 2 years ago
- A tool for checking the contract satisfaction for hardware designs☆12Updated this week
- Fast Symbolic Repair of Hardware Design Code☆39Jan 20, 2025Updated last year
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 3 years ago
- Exact Symbolic Reasoning via Boolean Equality Saturation☆25Jan 7, 2026Updated 6 months ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆31Dec 11, 2025Updated 7 months ago
- ☆15Jun 18, 2023Updated 3 years ago
- ☆27Apr 14, 2026Updated 3 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- UnityChip Verification AI-Agent☆192Jul 16, 2026Updated last week