Alternatives and similar repositories for VeriLogos

Users that are interested in VeriLogos are comparing it to the libraries listed below

• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆43Updated last year
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆27Updated 7 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• hkust-zhiyao / NetTAG
  NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
  ☆21Updated 3 months ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆40Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 6 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆66Updated 5 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 6 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆148Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• NVlabs / curvyILT
  ☆18Updated last month
• AutoBench / AutoBench
  ☆33Updated 7 months ago
• GATECH-EIC / mg-verilog
  ☆50Updated last year
• NVlabs / CircuitOps
  ☆92Updated 5 months ago
• achieve-lab / assertion_data_for_LLM
  ☆21Updated 10 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆33Updated 7 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆28Updated last year
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆39Updated last year
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆54Updated 10 months ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆75Updated 7 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆56Updated 5 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆36Updated 6 months ago
• zshi0616 / python-deepgate
  ☆26Updated last year
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆343Updated 4 months ago
• NVlabs / INSTA
  ☆89Updated 5 months ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆17Updated 11 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆38Updated last year
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆30Updated 5 months ago