Alternatives and similar repositories for VeriLogos

Users that are interested in VeriLogos are comparing it to the libraries listed below

• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆33Updated 10 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated 2 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆50Updated last year
• hkust-zhiyao / NetTAG
  NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
  ☆23Updated last month
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last month
• yaoxufeng / RTLRewriter-Bench
  ☆44Updated last year
• GATECH-EIC / mg-verilog
  ☆54Updated last year
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆15Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆35Updated last year
• AutoBench / AutoBench
  ☆36Updated 10 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆66Updated 8 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆155Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• NVlabs / curvyILT
  ☆21Updated 4 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated 3 weeks ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆86Updated 10 months ago
• pku-dasys / easymac
  ☆18Updated 4 years ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆59Updated last year
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆79Updated 8 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆56Updated last year
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆41Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆41Updated 8 months ago
• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆36Updated 7 months ago
• achieve-lab / assertion_data_for_LLM
  ☆23Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆35Updated 10 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆33Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• NVlabs / CircuitOps
  ☆97Updated 7 months ago
• shailja-thakur / VGen
  ☆199Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆80Updated 2 months ago