97kjmin / VeriLogosLinks
This repository includes the data and scripts utilized in the study titled "Improving LLM-based Verilog Code Generation with Data Augmentation and RL (DATE25)".
☆13Updated 10 months ago
Alternatives and similar repositories for VeriLogos
Users that are interested in VeriLogos are comparing it to the libraries listed below
Sorting:
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆32Updated 9 months ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆23Updated last month
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆49Updated last year
- This is a repo to store circuit design datasets☆19Updated 2 years ago
- This is a python repo for flattening Verilog☆20Updated last month
- ☆44Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- ☆54Updated last year
- ☆36Updated 9 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- An open-source benchmark for generating design RTL with natural language☆154Updated last year
- ☆59Updated 2 weeks ago
- ☆197Updated last year
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆78Updated 7 months ago
- ☆20Updated 3 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆58Updated last year
- ☆20Updated 3 years ago
- ☆33Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆86Updated 9 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆35Updated 9 months ago
- ☆53Updated 4 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Updated last year
- ☆23Updated last year
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆18Updated 4 months ago
- ☆97Updated 7 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆34Updated 7 months ago
- ☆33Updated last month
- ☆16Updated last year
- ☆18Updated 4 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆39Updated 8 months ago