Alternatives and similar repositories for EDA-schema

Users that are interested in EDA-schema are comparing it to the libraries listed below

• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• IntelLabs / FloorSet
  ☆77Updated 5 months ago
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆40Updated 5 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• ABKGroup / PROBE3.0
  ☆49Updated last year
• ABKGroup / RosettaStone
  ☆32Updated 3 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆28Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• scale-lab / ABACUS
  ABACUS is a tool for approximate logic synthesis
  ☆14Updated 5 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 6 months ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 6 years ago
• ChrisZonghaoLi / sky130_ldo_rl
  This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
  ☆45Updated last year
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆18Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆70Updated 2 weeks ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• NVlabs / INSTA
  ☆89Updated 5 months ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆18Updated 4 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆54Updated 10 months ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆40Updated 6 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆55Updated 6 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 7 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 10 months ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆28Updated 10 months ago