Random Generator of Btor2 Files
☆10Sep 2, 2023Updated 2 years ago
Alternatives and similar repositories for FuzzBtor2
Users that are interested in FuzzBtor2 are comparing it to the libraries listed below
Sorting:
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆11Jul 4, 2025Updated 7 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 3 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- ☆14Sep 14, 2020Updated 5 years ago
- A generic parser and tool package for the BTOR2 format.☆47Sep 18, 2025Updated 5 months ago
- ☆15Nov 9, 2022Updated 3 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Dec 23, 2025Updated 2 months ago
- ☆17Nov 19, 2023Updated 2 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14May 7, 2022Updated 3 years ago
- ☆19Jul 12, 2024Updated last year
- Equivalence checking with Yosys☆58Updated this week
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 7 months ago
- ☆14Jan 3, 2018Updated 8 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆14Apr 12, 2023Updated 2 years ago
- ☆14Jun 18, 2023Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- ☆15May 24, 2023Updated 2 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 3 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- ILA Model Database☆24Sep 27, 2020Updated 5 years ago
- Reads a state transition system and performs property checking☆90Sep 12, 2025Updated 5 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- Metal: Learning a Meta-Solver for Syntax-Guided Program Synthesis☆15Feb 18, 2019Updated 7 years ago
- Hardware Formal Verification Tool☆88Updated this week
- The HW-CBMC and EBMC Model Checkers for Verilog☆102Updated this week
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆64May 31, 2015Updated 10 years ago
- ☆16Jul 3, 2023Updated 2 years ago
- ☆20Jun 12, 2024Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆36Apr 3, 2025Updated 10 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 5 months ago
- ☆17Jul 11, 2021Updated 4 years ago