Alternatives and similar repositories for FuzzBtor2

Users that are interested in FuzzBtor2 are comparing it to the libraries listed below

• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 10 months ago
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆12Updated 2 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆64Updated last week
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆42Updated last week
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆29Updated 5 months ago
• mgudemann / iimc
  ☆14Updated 7 years ago
• iscas-tis / CHA
  ☆19Updated last year
• lijwen2748 / simplecar
  ☆15Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆36Updated last year
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆15Updated 3 years ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆85Updated this week
• amahzoon / genmul
  ☆17Updated 4 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆16Updated 6 years ago
• RafaelTupynamba / SMTSampler
  SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints
  ☆29Updated 5 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 4 years ago
• zilongwang123 / LeaVe
  A tool for checking the contract satisfaction for hardware designs
  ☆11Updated 9 months ago
• sterin / super-prove-build
  ☆13Updated 5 years ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆109Updated this week
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆15Updated last week
• efeslab / hardware-bugbase
  ☆18Updated last year
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated last week
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆13Updated 2 years ago
• arbrad / IC3ref
  IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.
  ☆59Updated 10 years ago