Alternatives and similar repositories for hierarchical-gnn-for-hls

Users that are interested in hierarchical-gnn-for-hls are comparing it to the libraries listed below

• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆51Updated last year
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 6 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 2 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 11 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 8 months ago
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆21Updated last year
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆35Updated 9 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated last month
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 4 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated last year
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• UCLA-DM / HLSyn
  HLSyn benchmark for paper "Towards a Comprehensive Benchmark for FPGA Targeted High-Level Synthesis"
  ☆29Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆36Updated last year
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆60Updated 9 months ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆22Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last week
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated 2 months ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆84Updated 2 years ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆16Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆86Updated last month
• RipperJ / FADO
  [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
  ☆24Updated 2 years ago