Alternatives and similar repositories for assertion_data_for_LLM

Users that are interested in assertion_data_for_LLM are comparing it to the libraries listed below

• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆29Updated 4 months ago
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆32Updated 7 months ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 10 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆62Updated 2 weeks ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• iscas-tis / CHA
  ☆19Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 10 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 2 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 3 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• ekiwi / simulator-independent-coverage
  Project Repo for the Simulator Independent Coverage Research
  ☆20Updated 2 years ago
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆11Updated last year
• bu-icsg / ProcessorFuzz
  ☆13Updated 11 months ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆34Updated 3 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 7 months ago
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆29Updated 6 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated last year
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆23Updated 2 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆36Updated last year
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• efeslab / hardware-bugbase
  ☆18Updated last year
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆72Updated last year
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆35Updated last year
• HWSec-UNC / Sylvia
  ☆18Updated 2 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago