Alternatives and similar repositories for assertion_data_for_LLM

Users that are interested in assertion_data_for_LLM are comparing it to the libraries listed below

• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆35Updated 9 months ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆35Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆48Updated last year
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆13Updated 2 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆32Updated 9 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆85Updated last week
• yaoxufeng / RTLRewriter-Bench
  ☆44Updated last year
• gpt4rtl / AutoSVA2
  ☆17Updated 2 years ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• fangwenji / tacas23-wasim
  ☆13Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆34Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆32Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆13Updated 2 years ago
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆14Updated 2 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆45Updated 4 months ago
• AutoBench / AutoBench
  ☆35Updated 9 months ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis
  ☆30Updated this week
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 9 months ago
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆36Updated 10 months ago
• AutoBench / CorrectBench
  ☆33Updated 3 weeks ago
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• zilongwang123 / LeaVe
  A tool for checking the contract satisfaction for hardware designs
  ☆12Updated 2 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆17Updated 7 years ago
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆75Updated 2 years ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆38Updated 7 months ago