Intelligent-Computing-Research-Group / HaVenLinks
[DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers
☆31Updated 5 months ago
Alternatives and similar repositories for HaVen
Users that are interested in HaVen are comparing it to the libraries listed below
Sorting:
- ☆53Updated 3 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆29Updated 8 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆241Updated 10 months ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆30Updated 5 months ago
- Fix syntax errors of LLM-generated RTL☆39Updated last year
- LLM4HWDesign Starting Toolkit☆18Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆75Updated 8 months ago
- ☆33Updated 8 months ago
- ☆39Updated 9 months ago
- This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.☆23Updated 6 months ago
- ☆54Updated 6 months ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)☆35Updated last week
- An open-source benchmark for generating design RTL with natural language☆150Updated last year
- Datasets for EDA LLM research☆35Updated 10 months ago
- ☆257Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆54Updated 11 months ago
- ☆84Updated 9 months ago
- ☆192Updated last year
- ☆33Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆34Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- Verilog evaluation benchmark for large language model☆350Updated 5 months ago
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆17Updated 2 months ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆21Updated last week
- ☆105Updated 3 months ago
- ☆18Updated 8 months ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆35Updated 6 months ago
- ☆15Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆141Updated 4 months ago