Alternatives and similar repositories for HaVen

Users that are interested in HaVen are comparing it to the libraries listed below

• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆23Updated 10 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆10Updated last month
• IPRC-DIP / CodeV
  ☆25Updated 3 weeks ago
• OpenROAD-Assistant / EDA-Corpus
  Datasets for EDA LLM research
  ☆23Updated 4 months ago
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆29Updated 11 months ago
• GATECH-EIC / LLM4HWDesign_Starting_Toolkit
  LLM4HWDesign Starting Toolkit
  ☆17Updated 7 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated 7 months ago
• shailja-thakur / AutoChip
  ☆27Updated 2 months ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆40Updated 4 months ago
• ACADLab / SPICEPilot
  This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.
  ☆14Updated 6 months ago
• lesliepy99 / RAG-EDA
  ☆13Updated last month
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆13Updated last month
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆27Updated 11 months ago
• iwls2020-lsml-contest / iwls2020-lsml-contest
  ☆21Updated 2 years ago
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆13Updated 11 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆29Updated 6 months ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 8 months ago
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆191Updated 3 months ago
• ACADLab / SA-DS
  ☆11Updated 9 months ago
• masc-ucsc / hdlagent
  LLM Agent for Hardware Description Language
  ☆20Updated last month
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• laiyao1 / AnalogCoder
  ☆56Updated last month
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆45Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 4 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• magicYang1573 / llm-hardware-test-generation
  ☆29Updated 10 months ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆28Updated last year
• laiyao1 / ArithmeticTree
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 7 months ago
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 2 months ago