Python version of tools to work with AIG formatted files
☆12May 20, 2025Updated last year
Alternatives and similar repositories for AIGER
Users that are interested in AIGER are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).☆50Dec 21, 2025Updated 7 months ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆30Dec 23, 2025Updated 6 months ago
- ☆19Dec 21, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 4 years ago
- ☆18Dec 30, 2023Updated 2 years ago
- AIGER And-Inverter-Graph Library☆105Feb 17, 2026Updated 5 months ago
- ☆18Feb 25, 2026Updated 4 months ago
- ☆10Oct 15, 2021Updated 4 years ago
- A generic parser and tool package for the BTOR2 format.☆49Sep 18, 2025Updated 10 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆18Nov 9, 2022Updated 3 years ago
- Verified graph rewriting (for dataflow circuits).☆25Updated this week
- Connecting bv_decide to SMTLIB.☆15Updated this week
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- ☆18May 24, 2023Updated 3 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 9 years ago
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- FOND4LTLf translates an LTLf/PLTLf-FOND to standard FOND planning problems☆17Nov 3, 2024Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆28Jul 12, 2023Updated 3 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- A Formal Verification Framework for Chisel☆21Apr 9, 2024Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆59Jan 8, 2025Updated last year
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆105Feb 27, 2026Updated 4 months ago
- Regular Invariant Generator and SMTLIB2 code transformer☆13Aug 8, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- GNN-RE datasets for circuit recognition☆59May 16, 2023Updated 3 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆93Jul 10, 2025Updated last year
- ☆18Jul 12, 2024Updated 2 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- A Lean-embedded framework to verify Verilog modules☆15Jul 3, 2026Updated 2 weeks ago
- Strix is a tool for reactive synthesis of controllers from LTL specifications.☆27Sep 16, 2022Updated 3 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆151Jul 23, 2025Updated 11 months ago