JKomp / AIGERLinks
Python version of tools to work with AIG formatted files
☆12Updated 6 months ago
Alternatives and similar repositories for AIGER
Users that are interested in AIGER are comparing it to the libraries listed below
Sorting:
- py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).☆49Updated 11 months ago
- ☆10Updated 4 years ago
- ☆18Updated 4 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 3 years ago
- Arithmetic multiplier benchmarks☆11Updated 8 years ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Updated last year
- ☆13Updated 4 years ago
- ☆12Updated 2 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆38Updated last year
- ☆14Updated 5 years ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- ☆19Updated last year
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Updated 6 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 7 months ago
- Integer Multiplier Generator for Verilog☆23Updated 4 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 5 months ago
- DATuner Repository☆17Updated 7 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆14Updated 3 years ago
- ☆13Updated 2 years ago
- BTOR2 MLIR project☆26Updated last year
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- ☆20Updated 3 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Updated 3 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆33Updated 7 months ago
- A generic parser and tool package for the BTOR2 format.☆45Updated 2 months ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- ☆16Updated 2 years ago
- Automatic generation of architecture-level models for hardware from its RTL design.☆14Updated 2 years ago