APS: An open-source toolchain towards agile processor specialization based on MLIR
☆20Jan 17, 2026Updated 7 months ago
Alternatives and similar repositories for aps-mlir
Users that are interested in aps-mlir are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Yosys RTLIL dialect for MLIR☆24Jun 12, 2025Updated last year
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆14Nov 2, 2023Updated 2 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A Lean-embedded framework to verify Verilog modules☆15Aug 15, 2026Updated 2 weeks ago
- ☆18Feb 25, 2026Updated 6 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- Source code for Trinity(ASPLOS 2026)☆26Apr 24, 2026Updated 4 months ago
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 7 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- AI-Assisted Verification of Data Structures☆22May 27, 2026Updated 3 months ago
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆21May 2, 2026Updated 3 months ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆16Oct 13, 2020Updated 5 years ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 8 months ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 9 months ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- CODO: An Automated Compiler for Comprehensive Dataflow Optimization☆36Jun 3, 2026Updated 2 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆24Oct 31, 2024Updated last year
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 7 months ago
- Python version of tools to work with AIG formatted files☆13May 20, 2025Updated last year
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆32May 24, 2025Updated last year
- ☆19Dec 21, 2020Updated 5 years ago
- ☆18Aug 9, 2025Updated last year
- Egraphs Modulo Theories☆20Jun 10, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Recent papers related to hardware formal verification.☆78Sep 20, 2023Updated 2 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated 2 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- A retargetable and extensible synthesis-based compiler for modern hardware architectures☆20Nov 20, 2025Updated 9 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- ☆49May 18, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆49May 29, 2025Updated last year