BUPT-GAMMA / PolarGate
☆10Updated 5 months ago
Alternatives and similar repositories for PolarGate:
Users that are interested in PolarGate are comparing it to the libraries listed below
- ☆28Updated last year
- ☆22Updated 9 months ago
- Research paper based on or related to ABC.☆32Updated 2 weeks ago
- ☆14Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 2 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆21Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆44Updated 6 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 7 months ago
- ☆15Updated 2 years ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆63Updated 5 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆16Updated 3 months ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆45Updated 2 weeks ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆11Updated last year
- DeepGate3 for ICCAD2024☆10Updated 8 months ago
- ☆28Updated 10 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated 2 weeks ago
- Collection of digital hardware modules & projects (benchmarks)☆51Updated 4 months ago
- GPU-based logic synthesis tool☆81Updated 8 months ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆22Updated 2 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆47Updated 9 months ago
- ☆25Updated 11 months ago
- ☆11Updated 9 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆124Updated 5 months ago
- The first version of TritonPart☆24Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆22Updated 8 months ago
- Artificial Netlist Generator☆37Updated last year
- Simple Python interface for ABC☆23Updated last year
- ☆11Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆44Updated 2 months ago