hisrg / PYNQ_CNN_Accelerator_Tutorial
中文:
☆95Updated 5 years ago
Alternatives and similar repositories for PYNQ_CNN_Accelerator_Tutorial:
Users that are interested in PYNQ_CNN_Accelerator_Tutorial are comparing it to the libraries listed below
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆108Updated 7 years ago
- PYNQ学习资料☆160Updated 5 years ago
- ☆43Updated 6 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆94Updated 6 years ago
- FPGA☆146Updated 7 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆167Updated 11 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆133Updated 5 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆36Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆69Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆235Updated 3 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆90Updated last year
- A DNN Accelerator implemented with RTL.☆63Updated last month
- achieve softmax in PYNQ with heterogeneous computing.☆62Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago
- using xilinx xc6slx45 to implement mnist net☆82Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆111Updated 4 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆177Updated 8 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆219Updated 6 years ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago