hisrg / PYNQ_CNN_Accelerator_TutorialLinks
中文:
☆107Updated 6 years ago
Alternatives and similar repositories for PYNQ_CNN_Accelerator_Tutorial
Users that are interested in PYNQ_CNN_Accelerator_Tutorial are comparing it to the libraries listed below
Sorting:
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆114Updated 8 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- FPGA Accelerator for CNN using Vivado HLS☆327Updated 4 years ago
- ☆48Updated 7 years ago
- PYNQ学习资料☆173Updated 6 years ago
- The second place winner for DAC-SDC 2020☆98Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- FPGA☆159Updated last year
- using xilinx xc6slx45 to implement mnist net☆84Updated 7 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆166Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆196Updated 8 years ago
- Pynq computer vision examples with an OV5640 camera☆57Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆247Updated 6 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 6 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago