AcceleratedCloud / SPynq
Spark on Pynq
☆45Updated 5 years ago
Alternatives and similar repositories for SPynq:
Users that are interested in SPynq are comparing it to the libraries listed below
- PYNQ, Neural network Language model, Overlay☆106Updated 5 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- ☆88Updated 4 years ago
- ☆44Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆70Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆109Updated 7 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- PYNQ学习资料☆162Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆135Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆91Updated last year
- A convolutional neural network implemented in hardware (verilog)☆157Updated 7 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- ☆246Updated 4 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆105Updated 4 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆266Updated 5 years ago
- Xilinx Deep Learning IP☆93Updated 3 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 3 years ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- DPU on PYNQ☆211Updated last year
- 中文:☆95Updated 5 years ago
- Python package which accelerates OpenCV image filtering functions for the PYNQ framework☆46Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- An LeNet RTL implement onto FPGA☆41Updated 6 years ago
- FPGA implementation of Cellular Neural Network (CNN)☆138Updated 6 years ago
- ☆27Updated 6 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- ☆63Updated 6 years ago