enjoy-digital / litex_verilog_axi_testLinks
Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
☆17Updated 2 years ago
Alternatives and similar repositories for litex_verilog_axi_test
Users that are interested in litex_verilog_axi_test are comparing it to the libraries listed below
Sorting:
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆12Updated 10 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- ☆32Updated last week
- ☆31Updated 5 years ago
- NoC based MPSoC☆11Updated 11 years ago
- ☆13Updated 9 months ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Basic floating-point components for RISC-V processors☆11Updated 8 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 11 months ago
- ☆38Updated 6 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆32Updated this week
- Design and UVM-TB of RISC -V Microprocessor☆30Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated 3 weeks ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 6 years ago
- ☆15Updated last month
- AHB Bus lite v3.0☆16Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 8 months ago
- ☆16Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago