Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
☆17Dec 19, 2022Updated 3 years ago
Alternatives and similar repositories for litex_verilog_axi_test
Users that are interested in litex_verilog_axi_test are comparing it to the libraries listed below
Sorting:
- ☆10May 26, 2023Updated 2 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- ☆41Apr 28, 2019Updated 6 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Build an open source, extremely simple DMA.☆23Feb 17, 2019Updated 7 years ago
- ☆11May 31, 2016Updated 9 years ago
- A verilog implementation for Network-on-Chip☆81Feb 3, 2018Updated 8 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Aug 8, 2019Updated 6 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- A GYD template for producing ZipSequences of arbitrary arity.☆10Nov 10, 2016Updated 9 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Oct 3, 2017Updated 8 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- ☆10Aug 15, 2019Updated 6 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- 200W 铝基板加热台控制器,具备PID控制,PWM输出,卡尔曼滤波☆11Oct 30, 2022Updated 3 years ago
- Clock Domain Crossing Design(use MCP formulation without feedback)基于MCP不带反馈的跨时钟域设计☆12Jan 3, 2020Updated 6 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- 使用verilog编写sdram控制器☆12Jun 22, 2019Updated 6 years ago
- MCP server for GNU Radio☆31Jan 5, 2026Updated 2 months ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- 一个开源的基于stm32的磁悬浮项目☆15Nov 21, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Xilinx AXI VIP example of use☆43Apr 24, 2021Updated 4 years ago
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 2 months ago
- ☆16Feb 23, 2025Updated last year
- This is a script for converting all Excel based formats to prettified XML format☆10Dec 13, 2017Updated 8 years ago
- FPGA code for NeTV2☆15Dec 3, 2018Updated 7 years ago
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆26Updated this week
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Wireless Industrial Condition Monitoring solution☆14Jan 17, 2025Updated last year
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago