enjoy-digital / litex_verilog_axi_testLinks
Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
☆16Updated 2 years ago
Alternatives and similar repositories for litex_verilog_axi_test
Users that are interested in litex_verilog_axi_test are comparing it to the libraries listed below
Sorting:
- ☆12Updated 4 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- double_fpu_verilog☆15Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 11 years ago
- ☆27Updated 3 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- OpenCores54x DSP☆9Updated 11 years ago
- ☆30Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆27Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- ☆30Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆14Updated 2 years ago
- AXI X-Bar☆19Updated 5 years ago
- ☆59Updated 3 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- ☆16Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆21Updated 5 years ago
- ☆33Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated this week
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago