patryk-oleniuk / cnn_hw_acceleratorLinks
FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
☆21Updated 6 years ago
Alternatives and similar repositories for cnn_hw_accelerator
Users that are interested in cnn_hw_accelerator are comparing it to the libraries listed below
Sorting:
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆47Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- ☆65Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆92Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- 中文:☆101Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 7 months ago
- FPGA/AES/LeNet/VGG16☆106Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆190Updated 7 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆36Updated 6 years ago
- An LeNet RTL implement onto FPGA☆49Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆186Updated last year
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- ☆113Updated 5 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 6 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆23Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago