hisrg / Neural-Network-Compression-and-Accelerator-on-HardwareLinks
My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, Cheng Du, China. For more informantion about me and my research, you can go to [my homepage](https://github.com/hisrg). One of my research interests is architecture design for deep learning and neuromorphic com…
☆53Updated 2 years ago
Alternatives and similar repositories for Neural-Network-Compression-and-Accelerator-on-Hardware
Users that are interested in Neural-Network-Compression-and-Accelerator-on-Hardware are comparing it to the libraries listed below
Sorting:
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆38Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- 2020 xilinx summer school☆18Updated 5 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- ☆21Updated 2 years ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- ☆30Updated 6 months ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 4 years ago
- ☆20Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆127Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆26Updated 3 years ago
- ☆71Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 8 months ago
- ☆35Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆91Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- ☆23Updated 3 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- Codes to implement MobileNet V2 in a FPGA☆27Updated 4 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- ☆18Updated 2 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago