Alternatives and similar repositories for Neural-Network-Compression-and-Accelerator-on-Hardware:

Users that are interested in Neural-Network-Compression-and-Accelerator-on-Hardware are comparing it to the libraries listed below

• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆36Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• heheda365 / ultra_net
  FPGA-based neural network inference project for 2020 DAC System Design Contest
  ☆111Updated 4 years ago
• xyzxinyizhang / 2019-DAC-System-Design-Contest
  ☆35Updated 5 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 2 years ago
• heymesut / SJTU_microe
  A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC
  ☆28Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆50Updated 3 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 5 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 3 years ago
• Anonymous788 / YOLO_BlockCir
  ☆32Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
  2020 xilinx summer school
  ☆17Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• ehw-fit / tf-approximate
  Approximate layers - TensorFlow extension
  ☆27Updated 10 months ago
• ignperez-udec / MobileNet-V2-inference-HLS
  Codes to implement MobileNet V2 in a FPGA
  ☆24Updated 4 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆49Updated 6 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 4 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆34Updated last year
• PSCLab-ASU / Systolic-CNN
  ☆15Updated 4 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆31Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆56Updated 3 years ago
• AiArtisan / dac_sdc_2022_champion
  ☆21Updated 2 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆36Updated 2 years ago
• isakedo / DNNsim
  ☆32Updated 4 years ago