drichmond / PYNQ-HLS
A Tutorial on Putting High-Level Synthesis cores in PYNQ
☆103Updated 6 years ago
Alternatives and similar repositories for PYNQ-HLS:
Users that are interested in PYNQ-HLS are comparing it to the libraries listed below
- PYNQ, Neural network Language model, Overlay☆105Updated 5 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆98Updated 2 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆68Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- ☆43Updated 6 years ago
- Vitis HLS Library for FINN☆189Updated last month
- ☆88Updated 4 years ago
- ☆60Updated 6 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- DPU on PYNQ☆208Updated last year
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆45Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- PYNQ Composabe Overlays☆70Updated 7 months ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆100Updated 4 years ago
- Board files to build Ultra 96 PYNQ image☆153Updated last month
- A FPGA Based CNN accelerator, following Google's TPU V1.☆130Updated 5 years ago
- RISC-V Integration for PYNQ☆167Updated 5 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆107Updated 7 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆147Updated 5 years ago
- ☆83Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- A convolutional neural network implemented in hardware (verilog)☆155Updated 7 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆111Updated 3 years ago
- ☆64Updated 2 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆89Updated last year