drichmond / PYNQ-HLSLinks
A Tutorial on Putting High-Level Synthesis cores in PYNQ
☆107Updated 7 years ago
Alternatives and similar repositories for PYNQ-HLS
Users that are interested in PYNQ-HLS are comparing it to the libraries listed below
Sorting:
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆108Updated 2 years ago
- DPU on PYNQ☆228Updated 2 months ago
- Vitis HLS Library for FINN☆208Updated 3 weeks ago
- PYNQ, Neural network Language model, Overlay☆111Updated 6 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 5 years ago
- Computer Vision Overlays on Pynq☆188Updated 6 years ago
- ☆250Updated 5 years ago
- ☆90Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- PYNQ Composabe Overlays☆73Updated last year
- Board files to build Ultra 96 PYNQ image☆157Updated last month
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- RISC-V Integration for PYNQ☆176Updated 6 years ago
- ☆70Updated 6 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆154Updated 5 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- Xilinx Deep Learning IP☆94Updated 4 years ago
- A convolutional neural network implemented in hardware (verilog)☆163Updated 8 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆161Updated 6 years ago
- ☆48Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- ☆132Updated last week
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆112Updated 7 years ago
- ☆117Updated 4 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆279Updated 5 years ago