Xilinx / LSTM-PYNQLinks
☆90Updated 5 years ago
Alternatives and similar repositories for LSTM-PYNQ
Users that are interested in LSTM-PYNQ are comparing it to the libraries listed below
Sorting:
- PYNQ, Neural network Language model, Overlay☆111Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- DPU on PYNQ☆228Updated 2 months ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆93Updated 6 years ago
- Xilinx Deep Learning IP☆94Updated 4 years ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆224Updated 6 years ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆279Updated 5 years ago
- An LSTM template and a few examples using Vivado HLS☆45Updated last year
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- ☆250Updated 5 years ago
- Vitis HLS Library for FINN☆208Updated 3 weeks ago
- Convolutional Neural Network Using High Level Synthesis☆88Updated 5 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- ☆109Updated 6 years ago
- ☆60Updated 5 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Updated 6 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- Computer Vision Overlays on Pynq☆188Updated 6 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- ☆70Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- Residual Binarized Neural Network☆42Updated 7 years ago
- This project is trying to create a base vitis platform to run with DPU☆48Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 6 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆112Updated 7 years ago