ZhaoqxCN / PYNQ-CNN-ATTEMPTLinks
Some attempts to build CNN on PYNQ.
☆25Updated 6 years ago
Alternatives and similar repositories for PYNQ-CNN-ATTEMPT
Users that are interested in PYNQ-CNN-ATTEMPT are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆89Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆189Updated last year
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆103Updated last year
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆88Updated 6 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆33Updated last year
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆68Updated 10 months ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆72Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆169Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆162Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆37Updated 3 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆47Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year