ZhaoqxCN / PYNQ-CNN-ATTEMPTLinks
Some attempts to build CNN on PYNQ.
☆25Updated 6 years ago
Alternatives and similar repositories for PYNQ-CNN-ATTEMPT
Users that are interested in PYNQ-CNN-ATTEMPT are comparing it to the libraries listed below
Sorting:
- Convolutional Neural Network Using High Level Synthesis☆90Updated 5 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆24Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 4 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 5 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆37Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆37Updated last year
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Updated last year
- An LeNet RTL implement onto FPGA☆51Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆36Updated 5 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆73Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆236Updated 2 years ago
- ☆123Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- Convolutional Neural Network RTL-level Design☆72Updated 4 years ago