Alternatives and similar repositories for coralnpu

Users that are interested in coralnpu are comparing it to the libraries listed below

• tiny-tpu-v2 / tiny-tpu
  A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
  ☆1,079Updated 4 months ago
• UCSBarchlab / OpenTPU
  A open source reimplementation of Google's Tensor Processing Unit (TPU).
  ☆718Updated 8 years ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,156Updated last week
• chipsalliance / t1
  ☆306Updated this week
• hughperkins / VeriGPU
  OpenSource GPU, in Verilog, loosely based on RISC-V ISA
  ☆1,158Updated last year
• jofrfu / tinyTPU
  Implementation of a Tensor Processing Unit for embedded systems and the IoT.
  ☆527Updated 6 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆395Updated 2 months ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆118Updated 6 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆481Updated last month
• aliemo / transfomers-silicon-research
  Research and Materials on Hardware implementation of Transformer Model
  ☆294Updated 10 months ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆284Updated 11 months ago
• Xilinx / mlir-aie
  An MLIR-based toolchain for AMD AI Engine-enabled devices.
  ☆550Updated this week
• intel / fpga-npu
  ☆230Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆455Updated this week
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆214Updated 6 years ago
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆183Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆689Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆631Updated last week
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆751Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆156Updated 10 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆309Updated last week
• Essenceia / Systolic_MAC_with_DFT
  GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure
  ☆28Updated 3 weeks ago
• cornell-zhang / allo
  Allo Accelerator Design and Programming Framework
  ☆316Updated this week
• tensil-ai / tensil
  Open source machine learning accelerators
  ☆393Updated last year
• google / CFU-Playground
  Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…
  ☆540Updated 9 months ago
• IBM / AccDNN
  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
  ☆436Updated 6 years ago
• eevaain / tiny-tpu-old
  A minimal Tensor Processing Unit (TPU) inspired by Google's TPUv1.
  ☆192Updated last year
• vortexgpgpu / vortex
  ☆1,829Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆533Updated last year