A machine learning accelerator core designed for energy-efficient AI at the edge.
☆2,485Jul 24, 2026Updated this week
Alternatives and similar repositories for coralnpu
Users that are interested in coralnpu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Berkeley's Spatial Array Generator☆1,406Jun 30, 2026Updated 3 weeks ago
- ☆2,173Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆933Jul 8, 2026Updated 3 weeks ago
- A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1☆1,355Apr 3, 2026Updated 3 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,344Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FSA: Fusing FlashAttention within a Single Systolic Array☆190Apr 15, 2026Updated 3 months ago
- CoralNPU behavior simulator based on MPACT-Sim☆25Jun 10, 2026Updated last month
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆209Jan 8, 2026Updated 6 months ago
- ☆28Feb 28, 2026Updated 5 months ago
- Chisel RISC-V Vector 1.0 Implementation☆153Jul 14, 2026Updated 2 weeks ago
- A Heterogeneous GPU Platform for AI and Neural Graphics☆65Jun 22, 2026Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆109Nov 26, 2025Updated 8 months ago
- Open-source high-performance RISC-V processor☆7,161Updated this week
- opensource NPU for LLM inference (this run gpt2)☆216Feb 16, 2026Updated 5 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆131Updated this week
- Repository to host and maintain SCALE-Sim code☆502Jun 28, 2026Updated last month
- OpenXuantie - OpenC910 Core☆1,458Jun 28, 2024Updated 2 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,201Jul 22, 2026Updated last week
- Chisel: A Modern Hardware Design Language☆4,740Updated this week
- Rocket Chip Generator☆3,826Jun 2, 2026Updated last month
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆532Jun 8, 2026Updated last month
- A minimal GPU design in Verilog to learn how GPUs work from the ground up☆12,780Aug 18, 2024Updated last year
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆662Aug 13, 2024Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Open, Modular, Deep Learning Accelerator☆356Apr 10, 2024Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆259Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆260Updated this week
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆58Jan 20, 2026Updated 6 months ago
- A Fast, Low-Overhead On-chip Network☆321Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆164Updated this week
- ASIC implementation flow infrastructure, successor to OpenLane☆490Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,638Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆111Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆355Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆1,989Updated this week
- OpenSource GPU, in Verilog, loosely based on RISC-V ISA☆1,355Nov 22, 2024Updated last year
- A fork of Xiangshan for AI☆56Updated this week
- Allo Accelerator Design and Programming Framework (PLDI'24)☆395Updated this week
- Open-source RTL logic simulator with CUDA acceleration☆288Sep 30, 2025Updated 9 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).☆247Updated this week