Alternatives and similar repositories for VeriGPU

Users that are interested in VeriGPU are comparing it to the libraries listed below

• vortexgpgpu / vortex
  ☆1,709Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,106Updated 4 years ago
• VerticalResearchGroup / miaow
  An open source GPU based off of the AMD Southern Islands ISA.
  ☆1,246Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆732Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆741Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆901Updated 2 years ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,646Updated last month
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,331Updated last year
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,659Updated last week
• rsd-devel / rsd
  RSD: RISC-V Out-of-Order Superscalar Processor
  ☆1,111Updated last week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,093Updated last week
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,554Updated 4 years ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆1,999Updated 2 weeks ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆956Updated last week
• jbush001 / NyuziProcessor
  GPGPU microprocessor architecture
  ☆2,131Updated 11 months ago
• riscv-software-src / riscv-tests
  ☆1,069Updated last week
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆810Updated 2 weeks ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,180Updated 3 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,130Updated 4 months ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,078Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,011Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆602Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆1,987Updated 5 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,468Updated 2 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated last month
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆863Updated last week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆428Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,204Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆936Updated 11 months ago