hughperkins / VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
☆952Updated 4 months ago
Alternatives and similar repositories for VeriGPU:
Users that are interested in VeriGPU are comparing it to the libraries listed below
- ☆1,455Updated last week
- 32-bit Superscalar RISC-V CPU☆972Updated 3 years ago
- An open source GPU based off of the AMD Southern Islands ISA.☆1,136Updated 7 years ago
- The OpenPiton Platform☆673Updated 2 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆669Updated 3 weeks ago
- OpenXuantie - OpenC910 Core☆1,237Updated 9 months ago
- ☆957Updated 3 weeks ago
- VeeR EH1 core☆864Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,500Updated last month
- RISC-V CPU Core (RV32IM)☆1,398Updated 3 years ago
- SERV - The SErial RISC-V CPU☆1,514Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,029Updated last month
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,056Updated 3 weeks ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,848Updated last week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆712Updated 2 weeks ago
- Modular hardware build system☆957Updated this week
- Random instruction generator for RISC-V processor verification☆1,081Updated last month
- SystemVerilog to Verilog conversion☆604Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆997Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆904Updated 4 months ago
- An open-source static random access memory (SRAM) compiler.☆883Updated 4 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,792Updated this week
- Common SystemVerilog components☆593Updated last week
- Linux on LiteX-VexRiscv☆620Updated 2 weeks ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆486Updated 4 months ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,414Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- Digital Design with Chisel☆818Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,242Updated last week
- RISC-V Cores, SoC platforms and SoCs☆867Updated 4 years ago