euphoric-hardware / rtl-simulation-readingLinks
☆18Updated last month
Alternatives and similar repositories for rtl-simulation-reading
Users that are interested in rtl-simulation-reading are comparing it to the libraries listed below
Sorting:
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- A hardware synthesis framework with multi-level paradigm☆43Updated 11 months ago
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- Fast Symbolic Repair of Hardware Design Code☆32Updated 11 months ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated last month
- ☆52Updated 11 months ago
- ILA Model Database☆24Updated 5 years ago
- ☆19Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆33Updated 4 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆34Updated 11 months ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆19Updated 10 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last week
- ☆17Updated 9 months ago
- This is a repo to store circuit design datasets☆19Updated last year
- Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)☆62Updated 3 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆40Updated 2 weeks ago
- Using e-graphs for logic synthesis☆29Updated last week
- DASS HLS Compiler☆29Updated 2 years ago
- ☆42Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- This is a python repo for flattening Verilog☆20Updated last week
- Equivalence checking with Yosys☆53Updated 3 weeks ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆27Updated 7 months ago
- Papers, Posters, Presentations, Documentation...☆19Updated last year
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆14Updated 2 years ago
- CGRA framework with vectorization support.☆42Updated this week
- ☆20Updated last year
- The OpenPiton Platform☆28Updated 2 years ago
- ☆17Updated 2 months ago