Alternatives and similar repositories for GEM

Users that are interested in GEM are comparing it to the libraries listed below

• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆115Updated 6 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆247Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆125Updated this week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆147Updated this week
• UCLA-VAST / RapidStream
  [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
  ☆126Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 3 months ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆126Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆219Updated 8 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆176Updated this week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆192Updated 5 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆112Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆165Updated last week
• bsc-loca / sargantana
  ☆115Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆228Updated this week
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆275Updated 2 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆275Updated 2 weeks ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆121Updated 2 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆198Updated last week
• The-OpenROAD-Project / asap7
  ☆216Updated 8 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last week
• tenstorrent / whisper
  ☆65Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆89Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 3 weeks ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆114Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆76Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆61Updated last week
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆195Updated last week