Open-source RTL logic simulator with CUDA acceleration
☆284Sep 30, 2025Updated 9 months ago
Alternatives and similar repositories for GEM
Users that are interested in GEM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GL0AM GPU Accelerated Gate Level Logic Simulator☆30Feb 11, 2026Updated 4 months ago
- ☆106Jun 20, 2025Updated last year
- GPU-based logic synthesis tool☆106Mar 31, 2026Updated 3 months ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- SpiceBind – spice inside HDL simulator☆58Jun 30, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog frontend for Yosys☆233Updated this week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated last year
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆32May 4, 2025Updated last year
- ☆31Apr 23, 2024Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- high-performance RTL simulator☆194Jun 19, 2024Updated 2 years ago
- ☆27Dec 8, 2025Updated 6 months ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 5 months ago
- ☆116Jun 22, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 6 months ago
- ☆49May 18, 2024Updated 2 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆29Apr 9, 2025Updated last year
- A standalone structural (gate-level) verilog parser☆41Mar 20, 2026Updated 3 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆41Apr 13, 2025Updated last year
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 11 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆38Jan 16, 2025Updated last year
- ☆14Aug 27, 2020Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- SystemVerilog compiler and language services☆1,078Jun 27, 2026Updated last week
- Research paper based on or related to ABC.☆72Jun 11, 2026Updated 3 weeks ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Library of FPGA architectures☆33Jun 22, 2026Updated last week
- Raptor end-to-end FPGA Compiler and GUI☆98Dec 11, 2024Updated last year
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated last year
- Verilog hardware abstraction library☆54Jun 26, 2026Updated last week
- Netlist API (and more) for EDA flow development☆143Jun 26, 2026Updated last week
- Communication framework for RTL simulation and emulation.☆316Jun 22, 2026Updated last week