Open-source RTL logic simulator with CUDA acceleration
☆307Sep 30, 2025Updated last year
Alternatives and similar repositories for GEM
Users that are interested in GEM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆113Jun 20, 2025Updated last year
- GL0AM GPU Accelerated Gate Level Logic Simulator☆33Feb 11, 2026Updated 8 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆126Apr 1, 2024Updated 2 years ago
- GPU-based logic synthesis tool☆111Mar 31, 2026Updated 7 months ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆91Oct 21, 2026Updated 2 weeks ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆23May 2, 2026Updated 6 months ago
- SystemVerilog compiler and language services☆1,175Updated this week
- Spire is a Python embedded domain-specific language (DSL) for RTL generation. Its built-in optimizations reduce area and delay of circuit…☆51Oct 13, 2026Updated 3 weeks ago
- SystemVerilog design elaborator into word-level netlist form☆253Updated this week
- Modular hardware build system☆1,239Updated this week
- Open source RTL simulation acceleration on commodity hardware☆37Apr 13, 2023Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆74Jun 28, 2025Updated last year
- Digital Design Equivalence Checking☆114Updated this week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Zhuofan Lin and Shiju Lin, "GPU-Accelerated Efficient Transduction for Logic Optimization", Design, Automation & Test in Europe Conferenc…☆14Sep 19, 2026Updated last month
- ☆91Updated this week
- Craft your EDA toolchain with GRH IR☆21Updated this week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆46Jul 17, 2024Updated 2 years ago
- high-performance RTL simulator☆196Aug 4, 2026Updated 2 months ago
- Yosys RTLIL dialect for MLIR☆25Jun 12, 2025Updated last year
- SystemVerilog synthesis tool☆237Mar 10, 2025Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Communication framework for RTL simulation and emulation.☆325Oct 26, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Research paper based on or related to ABC.☆75Jun 11, 2026Updated 4 months ago
- Circuit IR Compilers and Tools☆2,268Updated this week
- RTLMeter benchmark suite☆34Oct 26, 2026Updated last week
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆126Updated this week
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆72Apr 18, 2026Updated 6 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆22Jan 17, 2026Updated 9 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆148Oct 25, 2026Updated last week
- Verilog evaluation benchmark for large language model☆491Jul 14, 2025Updated last year
- A hardware verification framework in Rust, inspired by the UVM.☆14Oct 28, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- XLS: Accelerated HW Synthesis☆1,971Updated this week
- ☆62Oct 10, 2026Updated 3 weeks ago
- ☆102Jun 24, 2025Updated last year
- ☆31Apr 23, 2024Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆476Updated this week
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆36Oct 15, 2024Updated 2 years ago
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 9 months ago