Alternatives and similar repositories for Baremetal-NN

Users that are interested in Baremetal-NN are comparing it to the libraries listed below

• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆31Updated 11 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆109Updated this week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆129Updated this week
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆39Updated 3 weeks ago
• tum-ei-eda / muriscv-nn
  muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
  ☆85Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆117Updated this week
• hyoukjun / OpenSMART
  Public release
  ☆57Updated 6 years ago
• pulp-platform / redmule
  ☆73Updated last week
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆74Updated last week
• pulp-platform / ITA
  ☆47Updated 4 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated last year
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆89Updated 3 weeks ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆66Updated last year
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆35Updated last week
• tenstorrent / whisper
  ☆54Updated 3 weeks ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated 4 months ago
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆20Updated 3 years ago
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆183Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated last week
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆136Updated 2 months ago
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆43Updated 4 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆65Updated 7 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆101Updated this week
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• ucb-bar / virgo
  Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
  ☆36Updated 2 months ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆108Updated 2 years ago