Alternatives and similar repositories for mpact-riscv

Users that are interested in mpact-riscv are comparing it to the libraries listed below

• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 2 months ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated last week
• riscvarchive / riscv-CMOs
  ☆89Updated last month
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆49Updated 2 weeks ago
• google / verilogpp
  ☆17Updated last year
• chipsalliance / tilelink
  ☆35Updated 10 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 7 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆67Updated 3 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆52Updated 9 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆66Updated 3 weeks ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆37Updated last week
• riscv-software-src / riscv-ctg
  ☆41Updated 11 months ago
• google / skywater-pdk-libs-sky130_fd_pr
  Primitives for SKY130 provided by SkyWater.
  ☆27Updated last year
• chipsalliance / OmnixtendEndpoint
  Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
  ☆18Updated 5 months ago
• ucb-bar / testchipip
  ☆85Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆91Updated last month
• AlSaqr-platform / he-soc
  ☆32Updated last week
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆112Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated 2 weeks ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
  9 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆18Updated 2 years ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated 2 weeks ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆113Updated 4 months ago
• riscv / riscv-aia
  ☆96Updated last month
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆61Updated last week
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago