google / mpact-riscvLinks
☆27Updated last month
Alternatives and similar repositories for mpact-riscv
Users that are interested in mpact-riscv are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆117Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated this week
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆153Updated 2 months ago
- ☆17Updated last year
- RISC-V Verification Interface☆138Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated this week
- Self checking RISC-V directed tests☆119Updated 8 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- A modeling library with virtual components for SystemC and TLM simulators☆179Updated this week
- Simple runtime for Pulp platforms☆50Updated last week
- Automatic SystemVerilog linting in github actions with the help of Verible☆36Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- RISC-V System on Chip Template☆160Updated 5 months ago
- A libgloss replacement for RISC-V that supports HTIF☆43Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆154Updated last year
- ☆78Updated this week
- Home of the Advanced Interface Bus (AIB) specification.☆58Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- The specification for the FIRRTL language☆62Updated this week
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Updated 3 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆129Updated 8 months ago
- ☆89Updated 5 months ago