shioyadan / KonataLinks
Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases
☆503Updated last year
Alternatives and similar repositories for Konata
Users that are interested in Konata are comparing it to the libraries listed below
Sorting:
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆602Updated last year
- A Linux-capable RISC-V multicore for and by the world☆753Updated last month
- The OpenPiton Platform☆754Updated 3 months ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆481Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆554Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Updated last year
- RISC-V Formal Verification Framework☆620Updated 3 years ago
- RISC-V Torture Test☆206Updated last year
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆194Updated this week
- educational microarchitectures for risc-v isa☆728Updated 4 months ago
- Modeling Architectural Platform☆214Updated last week
- ☆362Updated 3 months ago
- ☆625Updated this week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- ☆191Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆371Updated 8 years ago
- ☆301Updated last month
- Flexible Intermediate Representation for RTL☆749Updated last year
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆326Updated 3 weeks ago
- Digital Design with Chisel☆889Updated last month
- Documentation for RISC-V Spike☆105Updated 7 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆629Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 3 months ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Common SystemVerilog components☆692Updated 2 weeks ago
- Chisel examples and code snippets☆265Updated 3 years ago
- ☆1,102Updated last month
- A template project for beginning new Chisel work☆680Updated 3 months ago
- SystemVerilog compiler and language services☆911Updated this week