Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases
☆547Apr 8, 2024Updated 2 years ago
Alternatives and similar repositories for Konata
Users that are interested in Konata are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,183Jun 29, 2026Updated last week
- A simple superscalar out-of-order RISC-V microprocessor☆251Feb 24, 2025Updated last year
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,194Jun 26, 2026Updated last week
- ☆324Jan 23, 2026Updated 5 months ago
- The official repository for the gem5 computer-system architecture simulator.☆2,687Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A Linux-capable RISC-V multicore for and by the world☆816Updated this week
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆733Jul 1, 2026Updated last week
- Random instruction generator for RISC-V processor verification☆1,320Apr 3, 2026Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆243Nov 20, 2024Updated last year
- Modeling Architectural Platform☆227Jun 30, 2026Updated last week
- ☆64Dec 4, 2022Updated 3 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,997Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆233Jun 20, 2026Updated 2 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆152Apr 23, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆379Updated this week
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 6 years ago
- gem5 configuration for intel's skylake micro-architecture☆55Jan 6, 2022Updated 4 years ago
- SystemC/TLM-2.0 Co-simulation framework☆299Jun 26, 2026Updated last week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,185Feb 11, 2026Updated 4 months ago
- ☆38Aug 31, 2024Updated last year
- Sail RISC-V model☆732Updated this week
- RISC-V Virtual Prototype☆191Dec 13, 2024Updated last year
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆490Aug 3, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- BaseJump STL: A Standard Template Library for SystemVerilog☆673Updated this week
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆741Updated this week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆39Dec 23, 2021Updated 4 years ago
- Rocket Chip Generator☆3,811Jun 2, 2026Updated last month
- ☆201Dec 14, 2023Updated 2 years ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆659Aug 13, 2024Updated last year
- ☆385Jun 14, 2026Updated 3 weeks ago
- Chisel: A Modern Hardware Design Language☆4,711Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,022Jun 26, 2026Updated last week
- RiVEC Bencmark Suite☆132Nov 27, 2024Updated last year
- Spike, a RISC-V ISA Simulator☆3,163Jun 26, 2026Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆187Apr 4, 2026Updated 3 months ago
- Modern co-simulation framework for RISC-V CPUs☆182Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆924Updated this week