Alternatives and similar repositories for Konata

Users that are interested in Konata are comparing it to the libraries listed below

• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆701Updated last month
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆429Updated last week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆602Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆284Updated last year
• ucb-bar / berkeley-hardfloat
  ☆326Updated 8 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆706Updated 2 weeks ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆577Updated 9 months ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆837Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆497Updated 3 months ago
• riscv-non-isa / riscv-arch-test
  ☆564Updated 3 weeks ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆176Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆879Updated 2 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated this week
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆273Updated 3 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆545Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆630Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,128Updated 3 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆190Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 5 months ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆714Updated 2 months ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 9 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated 2 weeks ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆728Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆251Updated 2 years ago