Alternatives and similar repositories for Konata

Users that are interested in Konata are comparing it to the libraries listed below

• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆588Updated last year
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆294Updated last year
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆734Updated last month
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆730Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆527Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 10 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated this week
• sparcians / map
  Modeling Architectural Platform
  ☆203Updated 3 weeks ago
• riscv-non-isa / riscv-arch-test
  ☆589Updated 3 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆462Updated last month
• ucb-bar / berkeley-hardfloat
  ☆343Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆859Updated last week
• SpinalHDL / NaxRiscv
  ☆295Updated last month
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆718Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆656Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆605Updated this week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆265Updated 3 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆158Updated 3 years ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆609Updated 3 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆395Updated 11 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆363Updated 8 years ago
• CMU-SAFARI / ramulator
  A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, …
  ☆656Updated 2 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆665Updated 2 months ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆304Updated 4 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆271Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆833Updated last week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆320Updated 9 months ago