Alternatives and similar repositories for chisel-lab

Users that are interested in chisel-lab are comparing it to the libraries listed below

• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆257Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆207Updated this week
• RV-BOSC / OpenNoC
  ☆184Updated last month
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆136Updated 2 years ago
• OSCPU / ysyxSoC
  ☆86Updated last week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆148Updated this week
• OSCPU / yosys-sta
  ☆78Updated 4 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• OSCPU / chisel-playground
  ☆67Updated 6 months ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆300Updated 7 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆169Updated this week
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆234Updated last year
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆180Updated 6 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆155Updated 3 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆70Updated 9 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆154Updated 9 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆178Updated 10 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆139Updated last year
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆453Updated 3 weeks ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆108Updated 6 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 8 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆336Updated 11 months ago