jlpteaching / dinocpuLinks
A teaching-focused RISC-V CPU design used at UC Davis
☆150Updated 2 years ago
Alternatives and similar repositories for dinocpu
Users that are interested in dinocpu are comparing it to the libraries listed below
Sorting:
- RiscyOO: RISC-V Out-of-Order Processor☆168Updated 5 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆112Updated last month
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Chisel examples and code snippets☆263Updated 3 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- RISC-V Torture Test☆204Updated last year
- Comment on the rocket-chip source code☆179Updated 7 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆236Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆105Updated last month
- ☆190Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- A Tiny Processor Core☆114Updated 5 months ago
- Documentation for RISC-V Spike☆105Updated 7 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- Modern co-simulation framework for RISC-V CPUs☆165Updated this week
- Provides dot visualizations of chisel/firrtl circuits☆122Updated 2 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 3 months ago
- RiVEC Bencmark Suite☆126Updated last year
- Run rocket-chip on FPGA☆76Updated last month
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆160Updated last year
- A dynamic verification library for Chisel.☆159Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆76Updated 3 weeks ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 3 months ago
- RISC-V Virtual Prototype☆182Updated last year