jlpteaching / dinocpuLinks
A teaching-focused RISC-V CPU design used at UC Davis
☆152Updated 2 years ago
Alternatives and similar repositories for dinocpu
Users that are interested in dinocpu are comparing it to the libraries listed below
Sorting:
- RiscyOO: RISC-V Out-of-Order Processor☆162Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated last month
- Chisel Learning Journey☆110Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆106Updated 4 months ago
- Chisel examples and code snippets☆259Updated 3 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆158Updated 3 years ago
- Wrapper for Rocket-Chip on FPGAs☆137Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 4 months ago
- Modern co-simulation framework for RISC-V CPUs☆157Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆210Updated 3 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 10 months ago
- RISC-V Torture Test☆197Updated last year
- Comment on the rocket-chip source code☆180Updated 6 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Vector Acceleration IP core for RISC-V*☆183Updated 4 months ago
- A Tiny Processor Core☆110Updated 2 months ago
- ☆189Updated last year
- ☆347Updated 3 weeks ago
- RISC-V Virtual Prototype☆177Updated 9 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- Modeling Architectural Platform☆206Updated this week
- Provides various testers for chisel users☆100Updated 2 years ago
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆183Updated last week
- Unit tests generator for RVV 1.0☆92Updated last week
- Run rocket-chip on FPGA☆76Updated 2 weeks ago
- Documentation for RISC-V Spike☆103Updated 6 years ago
- RiVEC Bencmark Suite☆123Updated 10 months ago
- Open-source high-performance non-blocking cache☆89Updated 2 weeks ago