efabless / ravennaLinks
32-bit RISC-V microcontroller
☆11Updated 3 years ago
Alternatives and similar repositories for ravenna
Users that are interested in ravenna are comparing it to the libraries listed below
Sorting:
- ☆14Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆13Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 5 months ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- ☆36Updated 9 months ago
- ☆17Updated 9 months ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 4 years ago
- Zero to ASIC group submission for MPW2☆13Updated 5 months ago
- Extended and external tests for Verilator testing☆16Updated this week
- ☆18Updated 10 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 7 months ago
- ☆12Updated 3 years ago
- Ubuntu scripts that are used for setting up your machine for Sky130 designs.☆18Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆29Updated 4 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆15Updated 5 months ago
- A current mode buck converter on the SKY130 PDK☆30Updated 4 years ago
- components and examples for creating radio ICs using the open skywater 130nm PDK☆19Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆31Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated 2 months ago
- Open Analog Design Environment☆24Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 9 months ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year
- SAR ADC on tiny tapeout☆42Updated 7 months ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago