mballance / clusterv-socLinks
Quad cluster of RISC-V cores with peripherals and local memory
☆24Updated 3 years ago
Alternatives and similar repositories for clusterv-soc
Users that are interested in clusterv-soc are comparing it to the libraries listed below
Sorting:
- YSYX RISC-V Project NJU Study Group☆16Updated 6 months ago
- ☆29Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- ☆56Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- Simple single-port AXI memory interface☆42Updated last year
- [UNRELEASED] FP div/sqrt unit for transprecision☆22Updated last year
- ☆10Updated 5 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Implementation of the PCIe physical layer☆45Updated last week
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- ☆34Updated 6 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- ☆25Updated 4 years ago
- AXI Interconnect☆50Updated 3 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago