mballance / clusterv-soc
Quad cluster of RISC-V cores with peripherals and local memory
☆23Updated 2 years ago
Alternatives and similar repositories for clusterv-soc:
Users that are interested in clusterv-soc are comparing it to the libraries listed below
- SoC Based on ARM Cortex-M3☆25Updated this week
- ☆37Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆19Updated 8 months ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- SystemVerilog modules and classes commonly used for verification☆44Updated last week
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆26Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 6 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- Simple single-port AXI memory interface☆37Updated 7 months ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- DMA Hardware Description with Verilog☆12Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- ☆50Updated 3 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- Connecting SystemC with SystemVerilog☆37Updated 12 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- ☆16Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆30Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago