stevehoover / warp-vLinks
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
☆243Updated 8 months ago
Alternatives and similar repositories for warp-v
Users that are interested in warp-v are comparing it to the libraries listed below
Sorting:
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆255Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆228Updated 2 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Updated last week
- SoC based on VexRiscv and ICE40 UP5K☆161Updated 10 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆275Updated 3 weeks ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆239Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆291Updated last month
- RISC-V microcontroller for embedded and FPGA applications☆190Updated this week
- Basic RISC-V CPU implementation in VHDL.☆172Updated 5 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆154Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆183Updated 8 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆331Updated 4 years ago
- 😎 A curated list of awesome RISC-V implementations☆142Updated 2 years ago
- ☆258Updated 3 years ago
- VeeR EL2 Core☆315Updated last month
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆172Updated this week
- RISC-V CPU Core☆405Updated 7 months ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- CORE-V Family of RISC-V Cores☆320Updated 11 months ago
- A 32-bit RISC-V soft processor☆320Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆224Updated 2 weeks ago
- Fabric generator and CAD tools.☆214Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Updated last month
- ☆305Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆334Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- Example designs showing different ways to use F4PGA toolchains.☆282Updated last year
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆312Updated 2 weeks ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year