stevehoover / warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
☆233Updated 3 weeks ago
Alternatives and similar repositories for warp-v:
Users that are interested in warp-v are comparing it to the libraries listed below
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆249Updated 3 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- RISC-V CPU Core☆317Updated 9 months ago
- SoC based on VexRiscv and ICE40 UP5K☆154Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- Ariane is a 6-stage RISC-V CPU☆133Updated 5 years ago
- VeeR EL2 Core☆268Updated last week
- CORE-V Family of RISC-V Cores☆246Updated last month
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆221Updated last year
- A utility for Composing FPGA designs from Peripherals☆173Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆172Updated 8 months ago
- ☆231Updated 2 years ago
- ☆169Updated last year
- Verilog implementation of a RISC-V core☆109Updated 6 years ago
- ☆279Updated 2 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆383Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated 2 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- Basic RISC-V CPU implementation in VHDL.☆165Updated 4 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆204Updated 5 months ago
- ☆131Updated last year
- 😎 A curated list of awesome RISC-V implementations☆134Updated 2 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆326Updated this week
- Fabric generator and CAD tools☆163Updated last month