wuhanstudio / picorv32_tang
A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
☆26Updated last year
Alternatives and similar repositories for picorv32_tang:
Users that are interested in picorv32_tang are comparing it to the libraries listed below
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆12Updated last year
- turbo 8051☆28Updated 7 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.☆12Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- USB 2.0 Device IP Core☆55Updated 7 years ago
- USB 1.1 Host and Function IP core☆20Updated 10 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆30Updated 4 years ago
- FPGA implementation of the 8051 Microcontroller (Verilog)☆47Updated 10 years ago
- ☆14Updated 5 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- SEA-S7_gesture recognition☆15Updated 4 years ago
- SDIO Device Verilog Core☆22Updated 6 years ago
- TCP/IP controlled VPI JTAG Interface.☆63Updated 2 weeks ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆43Updated 6 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- 8051 core☆102Updated 10 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆57Updated 2 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- QSPI for SoC☆19Updated 5 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库!☆11Updated 8 months ago
- A Voila-Jones face detector hardware implementation☆31Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆37Updated 8 months ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆21Updated 10 months ago
- UART 16550 core☆32Updated 10 years ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago