efabless / caravel_mpw-oneLinks
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
☆137Updated 3 years ago
Alternatives and similar repositories for caravel_mpw-one
Users that are interested in caravel_mpw-one are comparing it to the libraries listed below
Sorting:
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆115Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆155Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- FuseSoC standard core library☆147Updated 3 months ago
- Fabric generator and CAD tools.☆196Updated this week
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆141Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 5 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- ☆83Updated 2 years ago
- Yet Another RISC-V Implementation☆97Updated 11 months ago
- ☆112Updated 4 years ago
- SystemVerilog frontend for Yosys☆157Updated this week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- ☆79Updated this week
- SystemVerilog synthesis tool☆209Updated 6 months ago
- Experimental flows using nextpnr for Xilinx devices☆245Updated 11 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆108Updated 4 years ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- A utility for Composing FPGA designs from Peripherals☆184Updated 8 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- ☆136Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- An Open Source configuration of the Arty platform☆132Updated last year
- An automatic clock gating utility☆50Updated 4 months ago
- Verilog wishbone components☆117Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆293Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆277Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 10 months ago
- ☆43Updated 6 months ago