efabless / caravel_mpw-oneLinks
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
☆137Updated 3 years ago
Alternatives and similar repositories for caravel_mpw-one
Users that are interested in caravel_mpw-one are comparing it to the libraries listed below
Sorting:
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- Fabric generator and CAD tools.☆198Updated last week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- ☆80Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- Experimental flows using nextpnr for Xilinx devices☆245Updated 11 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 6 months ago
- SystemVerilog frontend for Yosys☆165Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆111Updated 4 years ago
- SystemVerilog synthesis tool☆211Updated 6 months ago
- ☆83Updated 2 years ago
- ☆112Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆140Updated last month
- ☆43Updated 7 months ago
- Yet Another RISC-V Implementation☆97Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆277Updated last year
- Arduino compatible Risc-V Based SOC☆156Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated 3 weeks ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 9 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- ☆137Updated 9 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- VeeR EL2 Core☆297Updated this week
- https://caravel-user-project.readthedocs.io☆218Updated 7 months ago