efabless / caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
☆134Updated 3 years ago
Alternatives and similar repositories for caravel_mpw-one:
Users that are interested in caravel_mpw-one are comparing it to the libraries listed below
- Standard Cell Library based Memory Compiler using FF/Latch cells☆143Updated 8 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- FuseSoC standard core library☆127Updated last month
- ☆77Updated last year
- Fabric generator and CAD tools☆162Updated 2 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- https://caravel-user-project.readthedocs.io☆193Updated 2 weeks ago
- Open-source FPGA research and prototyping framework.☆204Updated 7 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆137Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- VeeR EL2 Core☆266Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆78Updated this week
- ☆79Updated 2 years ago
- SystemVerilog synthesis tool☆180Updated this week
- Yet Another RISC-V Implementation☆89Updated 5 months ago
- An Open-Source Design and Verification Environment for RISC-V☆78Updated 3 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 5 months ago
- An Open Source configuration of the Arty platform☆127Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- ☆88Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- ☆110Updated 4 years ago
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 11 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆102Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆145Updated 4 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago