SeanZarzycki / openSPARC-FPU
ASIC Design of the openSPARC Floating Point Unit
☆13Updated 8 years ago
Alternatives and similar repositories for openSPARC-FPU:
Users that are interested in openSPARC-FPU are comparing it to the libraries listed below
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Open FPGA Modules☆23Updated 5 months ago
- Network on Chip for MPSoC☆26Updated last week
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆31Updated last month
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆23Updated 3 weeks ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆18Updated 10 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated last week
- ☆25Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆29Updated last year
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated 2 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆22Updated last month
- The memory model was leveraged from micron.☆22Updated 6 years ago
- ☆25Updated 3 years ago
- ☆16Updated 5 years ago
- ☆41Updated 6 years ago