efabless / caravelLinks
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
☆344Updated 5 months ago
Alternatives and similar repositories for caravel
Users that are interested in caravel are comparing it to the libraries listed below
Sorting:
- https://caravel-user-project.readthedocs.io☆215Updated 6 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆287Updated last month
- ☆339Updated 2 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆310Updated 5 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 9 months ago
- CORE-V Family of RISC-V Cores☆287Updated 6 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆351Updated this week
- VeeR EL2 Core☆294Updated 2 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆292Updated last week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆414Updated 2 years ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆156Updated last year
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated last month
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆590Updated this week
- Fabric generator and CAD tools.☆193Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆266Updated 4 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆323Updated 8 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆525Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆155Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆286Updated 3 months ago
- ☆112Updated 2 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 3 months ago
- ☆242Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆275Updated last week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆472Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆229Updated 3 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆583Updated last week
- Arduino compatible Risc-V Based SOC☆155Updated last year
- FOSS Flow For FPGA☆401Updated 7 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆187Updated 3 months ago