efabless / caravelLinks
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
☆377Updated 11 months ago
Alternatives and similar repositories for caravel
Users that are interested in caravel are comparing it to the libraries listed below
Sorting:
- https://caravel-user-project.readthedocs.io☆228Updated 11 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆332Updated 2 months ago
- ☆378Updated 2 years ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆309Updated 3 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆390Updated last month
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆463Updated 2 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆674Updated last week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆161Updated last year
- CORE-V Family of RISC-V Cores☆324Updated 11 months ago
- VeeR EL2 Core☆317Updated last month
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆334Updated last year
- Fabric generator and CAD tools.☆217Updated this week
- FOSS Flow For FPGA☆423Updated last year
- An open-source static random access memory (SRAM) compiler.☆1,000Updated 3 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆196Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆310Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆285Updated 5 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆568Updated 3 months ago
- ☆122Updated 2 years ago
- Example designs showing different ways to use F4PGA toolchains.☆283Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆292Updated last week
- A list of resources related to the open-source FPGA projects☆439Updated 3 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆559Updated this week
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆202Updated last month
- ASIC implementation flow infrastructure, successor to OpenLane☆276Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆357Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆317Updated this week
- Basic RISC-V Test SoC☆170Updated 6 years ago