PulseRain Reindeer - RISCV RV32I[M] Soft CPU
☆129Aug 28, 2019Updated 6 years ago
Alternatives and similar repositories for Reindeer
Users that are interested in Reindeer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SoftCPU/SoC engine-V☆56Mar 19, 2025Updated last year
- ☆64Dec 16, 2018Updated 7 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Dec 2, 2020Updated 5 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- Featherweight RISC-V implementation☆53Jan 17, 2022Updated 4 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- Yet Another RISC-V Implementation☆99Sep 21, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- ☆14Oct 19, 2019Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- RISC-V CPU Core☆417Jun 24, 2025Updated 9 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,804Feb 17, 2026Updated last month
- SERV - The SErial RISC-V CPU☆1,766Feb 19, 2026Updated last month
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆228Aug 25, 2020Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆83Oct 11, 2019Updated 6 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- RISC-V CPU Core (RV32IM)☆1,668Sep 18, 2021Updated 4 years ago
- PulseRain Rattlesnake - RISCV RV32IMC Soft CPU☆34Nov 3, 2019Updated 6 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,501Jan 7, 2026Updated 2 months ago
- LatticeMico32 soft processor☆106Oct 10, 2014Updated 11 years ago
- ☆35Mar 8, 2023Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,526Dec 8, 2025Updated 3 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆654Jan 19, 2026Updated 2 months ago
- A 32-bit RISC-V soft processor☆322Jan 26, 2026Updated last month
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆289Jul 28, 2020Updated 5 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 2 years ago
- The memory model was leveraged from micron.☆29Mar 24, 2018Updated 8 years ago
- An open-source microcontroller system based on RISC-V☆1,017Feb 6, 2024Updated 2 years ago
- Naive Educational RISC V processor☆94Oct 12, 2025Updated 5 months ago
- Nitro USB FPGA core☆86Mar 1, 2026Updated 3 weeks ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago