Alternatives and similar repositories for Reindeer

Users that are interested in Reindeer are comparing it to the libraries listed below

• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆123Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆140Updated 6 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆90Updated last week
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆139Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆87Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆150Updated last year
• jamieiles / uart
  Verilog UART
  ☆178Updated 12 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆76Updated 2 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆90Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆57Updated 9 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆273Updated 5 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆151Updated 3 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆150Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 11 months ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆174Updated 6 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆139Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆126Updated 2 years ago
• freecores / i2c
  I2C controller core
  ☆47Updated 2 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆153Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago