Alternatives and similar repositories for netgen

Users that are interested in netgen are comparing it to the libraries listed below

• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• efabless / chipignite-resources
  ☆85Updated 3 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆44Updated 2 years ago
• parallaxsw / OpenSTA
  ☆97Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆174Updated 4 months ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆88Updated 8 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆67Updated last month
• efabless / mpw_precheck
  ☆44Updated 10 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆43Updated last week
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• chipfoundry / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆74Updated last month
• google / sky90fd-pdk
  ☆122Updated 2 years ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆51Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆184Updated last week
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆49Updated 3 months ago
• efabless / foss-asic-tools
  FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…
  ☆104Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 11 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆77Updated 9 months ago
• idea-fasoc / fasoc
  ☆57Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆41Updated 2 years ago
• ncsu-eda / FreePDK3
  ☆183Updated 4 years ago
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆46Updated 5 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆67Updated 6 months ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆90Updated 2 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆118Updated 4 years ago