Alternatives and similar repositories for qflow

Users that are interested in qflow are comparing it to the libraries listed below

• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆346Updated last week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆284Updated last month
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆154Updated last month
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆306Updated 5 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆343Updated 5 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated last week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆211Updated 5 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆285Updated 2 months ago
• ncsu-eda / FreePDK3
  ☆157Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆403Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆163Updated 2 months ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆161Updated 2 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆292Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆192Updated last week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆336Updated this week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆215Updated 3 weeks ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆221Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆206Updated 4 months ago
• rubund / graywolf
  ☆112Updated 4 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆121Updated 2 months ago
• google / sky90fd-pdk
  ☆112Updated 2 years ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆257Updated last week
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆557Updated this week
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆468Updated this week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆330Updated this week
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆410Updated 2 years ago
• efabless / chipignite-resources
  ☆81Updated 2 years ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last month
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆181Updated 5 years ago