Qflow full end-to-end digital synthesis flow for ASIC designs
☆235Oct 26, 2024Updated last year
Alternatives and similar repositories for qflow
Users that are interested in qflow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Qrouter detail router for digital ASIC designs☆59Nov 13, 2025Updated 9 months ago
- ☆112Feb 2, 2021Updated 5 years ago
- Magic VLSI Layout Tool☆695Updated this week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆142Jul 7, 2026Updated last month
- XCircuit circuit drawing and schematic capture tool☆145Jul 27, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An open-source static random access memory (SRAM) compiler.☆1,122Aug 16, 2026Updated 2 weeks ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,921Mar 25, 2026Updated 5 months ago
- OpenSTA engine☆610Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆443Updated this week
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆3,039Updated this week
- IRSIM switch-level simulator for digital circuits☆39Nov 13, 2025Updated 9 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆169Apr 1, 2026Updated 4 months ago
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,678Jul 21, 2026Updated last month
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Yosys Open SYnthesis Suite☆4,718Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆714Dec 26, 2025Updated 8 months ago
- An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.☆31Oct 25, 2020Updated 5 years ago
- A complete open-source design-for-testing (DFT) Solution☆203Aug 30, 2025Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆155Mar 17, 2023Updated 3 years ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- KLayout Main Sources☆1,182Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆407Feb 26, 2025Updated last year
- SystemVerilog to Verilog conversion☆749Aug 18, 2026Updated last week
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,259Updated this week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆138Feb 22, 2022Updated 4 years ago
- ☆63Jul 11, 2025Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆295Jun 18, 2026Updated 2 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,012Aug 23, 2026Updated last week
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 4 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆369Dec 2, 2025Updated 8 months ago
- ☆18Nov 4, 2024Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆297Jul 28, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An Open-source FPGA IP Generator☆1,141Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- Coriolis VLSI EDA Tool (LIP6)☆93Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆325Aug 7, 2026Updated 3 weeks ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆489Updated this week
- nextpnr portable FPGA place and route tool☆1,740Updated this week
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 5 years ago