Qflow full end-to-end digital synthesis flow for ASIC designs
☆236Oct 26, 2024Updated last year
Alternatives and similar repositories for qflow
Users that are interested in qflow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Qrouter detail router for digital ASIC designs☆60Nov 13, 2025Updated 10 months ago
- ☆112Feb 2, 2021Updated 5 years ago
- Magic VLSI Layout Tool☆704Updated this week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆142Jul 7, 2026Updated 2 months ago
- XCircuit circuit drawing and schematic capture tool☆145Jul 27, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An open-source static random access memory (SRAM) compiler.☆1,136Aug 16, 2026Updated last month
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,940Mar 25, 2026Updated 5 months ago
- OpenSTA engine☆619Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆453Updated this week
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆3,112Updated this week
- IRSIM switch-level simulator for digital circuits☆39Nov 13, 2025Updated 10 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆170Apr 1, 2026Updated 5 months ago
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,713Jul 21, 2026Updated last month
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Nov 13, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Yosys Open SYnthesis Suite☆4,761Updated this week
- A High-performance Timing Analysis Tool for VLSI Systems☆716Dec 26, 2025Updated 8 months ago
- An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.☆31Oct 25, 2020Updated 5 years ago
- A complete open-source design-for-testing (DFT) Solution☆204Aug 30, 2025Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆155Mar 17, 2023Updated 3 years ago
- Copyleftist's Standard Cell Library☆105May 2, 2024Updated 2 years ago
- KLayout Main Sources☆1,202Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆412Feb 26, 2025Updated last year
- SystemVerilog to Verilog conversion☆753Aug 18, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,267Updated this week
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆138Feb 22, 2022Updated 4 years ago
- ☆65Jul 11, 2025Updated last year
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆296Jun 18, 2026Updated 3 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆1,017Sep 3, 2026Updated 2 weeks ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆38Apr 9, 2026Updated 5 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆373Dec 2, 2025Updated 9 months ago
- ☆18Nov 4, 2024Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆297Jul 28, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open-source FPGA IP Generator☆1,153Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆269Updated this week
- Coriolis VLSI EDA Tool (LIP6)☆93Aug 28, 2026Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆326Aug 7, 2026Updated last month
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆493Updated this week
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 5 years ago
- nextpnr portable FPGA place and route tool☆1,753Updated this week