RTimothyEdwards / qflowLinks
Qflow full end-to-end digital synthesis flow for ASIC designs
☆223Updated last year
Alternatives and similar repositories for qflow
Users that are interested in qflow are comparing it to the libraries listed below
Sorting:
- Fully Open Source FASOC generators built on top of open-source EDA tools☆302Updated last month
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆377Updated last week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated 2 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- https://caravel-user-project.readthedocs.io☆224Updated 9 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- ☆183Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆369Updated 9 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆352Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆240Updated this week
- Fabric generator and CAD tools.☆214Updated this week
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- ☆122Updated 2 years ago
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆278Updated 5 years ago
- SystemRDL 2.0 language compiler front-end☆268Updated 3 weeks ago
- SystemVerilog synthesis tool☆220Updated 9 months ago
- ☆366Updated 2 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆298Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated 2 weeks ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆126Updated last week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆195Updated 5 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆198Updated last month
- VeeR EL2 Core☆310Updated this week
- UVM 1.2 port to Python☆256Updated 10 months ago
- ☆114Updated 4 years ago
- SystemVerilog frontend for Yosys☆181Updated this week