Alternatives and similar repositories for qflow:

Users that are interested in qflow are comparing it to the libraries listed below

• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆311Updated last month
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆264Updated 3 weeks ago
• ncsu-eda / FreePDK3
  ☆136Updated 3 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆265Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆275Updated 2 weeks ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆193Updated 2 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆143Updated 8 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated last week
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆247Updated 2 weeks ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆164Updated 5 years ago
• rubund / graywolf
  ☆110Updated 4 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆308Updated this week
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆441Updated 2 weeks ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆156Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆211Updated this week
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆385Updated this week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆102Updated 3 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆318Updated 2 weeks ago
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆515Updated 2 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆162Updated 2 weeks ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆145Updated 4 months ago
• google / sky90fd-pdk
  ☆109Updated last year
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆217Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆375Updated 2 months ago
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• StefanSchippers / xschem
  A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…
  ☆366Updated this week
• google / gf180mcu-pdk
  PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
  ☆385Updated last year
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆205Updated this week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 3 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week