Alternatives and similar repositories for qflow

Users that are interested in qflow are comparing it to the libraries listed below

• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆330Updated last week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆280Updated 2 weeks ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆254Updated 3 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆147Updated 11 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated 3 weeks ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆292Updated 3 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆281Updated 2 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆330Updated 3 months ago
• ncsu-eda / FreePDK3
  ☆146Updated 3 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆324Updated this week
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆185Updated last week
• rubund / graywolf
  ☆113Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆194Updated 2 months ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆177Updated 5 years ago
• google / sky90fd-pdk
  ☆111Updated 2 years ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆135Updated 3 years ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆455Updated 3 weeks ago
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆471Updated this week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆159Updated 2 years ago
• efabless / chipignite-resources
  ☆78Updated 2 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆322Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆153Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆278Updated 2 weeks ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆201Updated 3 months ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆117Updated 2 weeks ago
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆432Updated this week