RTimothyEdwards / magicLinks
Magic VLSI Layout Tool
☆564Updated this week
Alternatives and similar repositories for magic
Users that are interested in magic are comparing it to the libraries listed below
Sorting:
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆406Updated this week
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆602Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆354Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 10 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆312Updated 6 months ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆655Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆417Updated 2 years ago
- An open-source static random access memory (SRAM) compiler.☆948Updated 2 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆288Updated 2 months ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆488Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆347Updated 6 months ago
- ☆343Updated 2 years ago
- OpenSTA engine☆504Updated last week
- SystemVerilog to Verilog conversion☆663Updated 2 months ago
- FOSS Flow For FPGA☆405Updated 8 months ago
- An abstraction library for interfacing EDA tools☆710Updated 2 weeks ago
- https://caravel-user-project.readthedocs.io☆216Updated 6 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆156Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆467Updated last week
- The Xyce™ Parallel Electronic Simulator☆82Updated 2 weeks ago
- A list of resources related to the open-source FPGA projects☆425Updated 2 years ago
- Verilog to Routing -- Open Source CAD Flow for FPGA Research☆1,139Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆642Updated last week
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,571Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆1,157Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆406Updated 2 weeks ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆825Updated 2 months ago
- lowRISC Style Guides☆453Updated 3 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆605Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆416Updated last week