RTimothyEdwards / magic
Magic VLSI Layout Tool
☆515Updated 2 weeks ago
Alternatives and similar repositories for magic:
Users that are interested in magic are comparing it to the libraries listed below
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆366Updated this week
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆311Updated last month
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆479Updated this week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆201Updated 4 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆264Updated 3 weeks ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆275Updated 2 weeks ago
- An open-source static random access memory (SRAM) compiler.☆877Updated 3 months ago
- OpenSTA engine☆441Updated 2 weeks ago
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆385Updated last year
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆385Updated this week
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆436Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆318Updated 2 weeks ago
- https://caravel-user-project.readthedocs.io☆193Updated 2 weeks ago
- ☆286Updated this week
- ☆314Updated last year
- FOSS Flow For FPGA☆375Updated 2 months ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆147Updated 9 months ago
- Modular hardware build system☆940Updated this week
- The Xyce™ Parallel Electronic Simulator☆36Updated last week
- Multi-platform nightly builds of open source digital design and verification tools☆978Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 11 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,440Updated 2 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆429Updated last week
- A High-performance Timing Analysis Tool for VLSI Systems☆592Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆558Updated this week
- A list of resources related to the open-source FPGA projects☆398Updated 2 years ago
- A Linux-capable RISC-V multicore for and by the world☆666Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆308Updated this week
- An abstraction library for interfacing EDA tools☆668Updated this week