VGuoGavin / Hand-Writing-Digital-Recognization-Based-on-FPGA
Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.
☆10Updated 2 years ago
Alternatives and similar repositories for Hand-Writing-Digital-Recognization-Based-on-FPGA:
Users that are interested in Hand-Writing-Digital-Recognization-Based-on-FPGA are comparing it to the libraries listed below
- SoC Based on ARM Cortex-M3☆29Updated 2 weeks ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- ☆31Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- ☆25Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- ☆19Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- DMA controller for CNN accelerator☆13Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- ☆45Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆8Updated last year
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 9 months ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 8 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago