akukulanski / cnn
This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to make good use of the tools I enjoy the most for digital design. These include nmigen, cocotb, yosys, icarus verilog, gtkwave.
☆13Updated 4 years ago
Alternatives and similar repositories for cnn:
Users that are interested in cnn are comparing it to the libraries listed below
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- APB Logic☆17Updated 3 months ago
- NoC based MPSoC☆10Updated 10 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated 2 weeks ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 9 months ago
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 8 months ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- CNN accelerator☆28Updated 7 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆11Updated last month
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆26Updated 5 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Open-Source HLS Examples for Microchip FPGAs☆43Updated this week
- DMA controller for CNN accelerator☆13Updated 7 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆13Updated 5 years ago
- Audio filtering with pyfda and cocotb☆10Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆15Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆33Updated 4 years ago
- ☆8Updated last year
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- ☆12Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago