Charmve / AccANNLinks
🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
☆19Updated last year
Alternatives and similar repositories for AccANN
Users that are interested in AccANN are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆20Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆14Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆23Updated 3 years ago
- ☆26Updated 2 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆15Updated 2 years ago
- ☆17Updated 2 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆10Updated 3 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- EE 272B - VLSI Design Project☆12Updated 3 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆21Updated 2 years ago
- ☆14Updated 5 years ago
- Digital Design Lab Spring 2019 Final Project☆11Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆12Updated 2 years ago