Charmve / AccANN
🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
☆18Updated 9 months ago
Alternatives and similar repositories for AccANN:
Users that are interested in AccANN are comparing it to the libraries listed below
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆14Updated 3 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆8Updated 3 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- cnn accelerator in vivado HLS☆9Updated 3 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆23Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- ☆20Updated 2 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆49Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆13Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆40Updated 5 months ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆32Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- Fully Hardware-Based Stochastic Neural Network☆20Updated last month
- ☆26Updated 2 years ago
- A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA☆17Updated 2 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- ☆10Updated 3 months ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago