🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*
☆22May 27, 2024Updated 2 years ago
Alternatives and similar repositories for AccANN
Users that are interested in AccANN are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- CUDA实现'huawei-noah/AdderNet'的forward和backward☆17Apr 16, 2020Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 6 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆15Jun 28, 2021Updated 5 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆15Aug 26, 2021Updated 5 years ago
- ☆35Mar 1, 2019Updated 7 years ago
- ☆18Nov 20, 2022Updated 3 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Jul 17, 2017Updated 9 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆19Feb 27, 2021Updated 5 years ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆23Oct 26, 2022Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆200Mar 20, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆11Aug 27, 2021Updated 5 years ago
- OpenTitan FI formal verification framework☆18Aug 29, 2023Updated 3 years ago
- A 2D convolution hardware implementation written in Verilog☆53Dec 21, 2020Updated 5 years ago
- ☆20Nov 14, 2022Updated 3 years ago
- SplitSR: An End-to-End Approach to Super-Resolution on Mobile Devices (Unofficial Implementation)☆28Jan 24, 2021Updated 5 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆34Jun 8, 2022Updated 4 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆452Dec 2, 2019Updated 6 years ago
- Unaligned Guided Thermal Super-Resolution☆22May 25, 2022Updated 4 years ago
- Fully Hardware-Based Stochastic Neural Network☆23Jan 23, 2025Updated last year
- ☆14Aug 8, 2022Updated 4 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- CNN simd based accelerator using Vitis HLS☆12Jul 15, 2022Updated 4 years ago
- System Verilog code describing a fully combinational binarized neural network.☆36Jul 6, 2018Updated 8 years ago
- ☆27Nov 4, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 6 years ago
- VORNet: Spatio-temporally Consistent Video Inpainting for Object Removal, CVPRW 2019☆12Jul 18, 2019Updated 7 years ago
- We open-source our layout level fast EM simulation tool, EMSim, to the public.☆16Feb 8, 2024Updated 2 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- This program can render audio files as spectrograms and convert spectrograms back to audio.☆14Sep 17, 2015Updated 11 years ago
- ☆17Apr 16, 2024Updated 2 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago