yayouz / CNN-acceleratorLinks
DMA controller for CNN accelerator
☆14Updated 8 years ago
Alternatives and similar repositories for CNN-accelerator
Users that are interested in CNN-accelerator are comparing it to the libraries listed below
Sorting:
- RTL code for the DPU chip designed for irregular graphs☆13Updated 3 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- ☆40Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- ☆11Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20Updated 8 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Updated 3 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Updated 2 years ago
- ☆29Updated 6 years ago
- ☆15Updated 3 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated last year
- ☆73Updated 7 years ago
- Tensor Processing Unit implementation in Verilog☆13Updated 10 months ago
- NoC based MPSoC☆11Updated 11 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 5 years ago
- ☆31Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆65Updated 3 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆40Updated 8 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆31Updated last year