yayouz / CNN-acceleratorLinks
DMA controller for CNN accelerator
☆13Updated 8 years ago
Alternatives and similar repositories for CNN-accelerator
Users that are interested in CNN-accelerator are comparing it to the libraries listed below
Sorting:
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆15Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- ☆34Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- ☆29Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 6 years ago
- ☆27Updated 5 years ago
- ☆14Updated 2 years ago
- ☆20Updated 2 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 4 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- ☆10Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 7 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆26Updated 4 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆33Updated 10 months ago