yayouz / CNN-accelerator
DMA controller for CNN accelerator
☆13Updated 7 years ago
Alternatives and similar repositories for CNN-accelerator:
Users that are interested in CNN-accelerator are comparing it to the libraries listed below
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆14Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- ☆9Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- ☆31Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- ☆26Updated 5 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- ☆14Updated last year
- verification of simple axi-based cache☆18Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- A systolic array matrix multiplier☆24Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- ☆19Updated 2 years ago
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- ☆26Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year