Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
☆62Nov 23, 2021Updated 4 years ago
Alternatives and similar repositories for ResNet50-PYNQ
Users that are interested in ResNet50-PYNQ are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vitis HLS Library for FINN☆227May 27, 2026Updated 3 months ago
- Dataflow compiler for QNN inference on FPGAs☆1,045Updated this week
- DPU on PYNQ☆248Aug 12, 2025Updated last year
- Dataflow QNN inference accelerator examples on FPGAs☆263Mar 10, 2026Updated 5 months ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆110Jun 30, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Train and deploy LUT-based neural networks on FPGAs☆120Jun 12, 2024Updated 2 years ago
- ☆74Feb 16, 2023Updated 3 years ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Jun 27, 2019Updated 7 years ago
- ☆10Mar 20, 2021Updated 5 years ago
- Deployment of Deep learning Image Super-Resolution Models in Xilinx Zynq MPSoC ZCU102☆19May 30, 2020Updated 6 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆36Oct 4, 2023Updated 2 years ago
- ☆37Jun 1, 2022Updated 4 years ago
- ☆14Aug 14, 2023Updated 3 years ago
- The Riallto Open Source Project from AMD☆87Apr 10, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Introductory examples for using PYNQ with Alveo☆54Mar 14, 2023Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆41May 17, 2022Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- ☆20Sep 15, 2021Updated 4 years ago
- Source files for Getting to Know Vivado course☆18Sep 2, 2020Updated 5 years ago
- ☆67May 6, 2020Updated 6 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆705Jan 4, 2022Updated 4 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- 32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss dat…☆15Aug 20, 2026Updated last week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Jupyter notebook examples on image classification with quantized neural networks☆70May 5, 2020Updated 6 years ago
- Projects and Labs for the Parallel Programming for FPGAs book☆24Dec 3, 2025Updated 8 months ago
- Brevitas: neural network quantization in PyTorch☆1,567Updated this week
- Provides Spatial with front-end support from popular machine learning frameworks☆34Sep 30, 2019Updated 6 years ago
- Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices☆12Jul 1, 2021Updated 5 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆388Jan 20, 2025Updated last year
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- ☆30Apr 26, 2019Updated 7 years ago
- ☆18Jan 22, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆65Nov 7, 2019Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Jan 3, 2023Updated 3 years ago
- muSYCL, the SYCL musical!☆13Aug 25, 2024Updated 2 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆343Jan 20, 2025Updated last year
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆150Dec 25, 2019Updated 6 years ago
- Python Productivity for ZYNQ☆2,341Updated this week