Xilinx / ResNet50-PYNQ
Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
☆57Updated 3 years ago
Alternatives and similar repositories for ResNet50-PYNQ:
Users that are interested in ResNet50-PYNQ are comparing it to the libraries listed below
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆71Updated 2 years ago
- ☆70Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆85Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆44Updated 10 months ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 5 years ago
- ☆57Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- Vitis HLS Library for FINN☆191Updated 3 weeks ago
- ☆87Updated 9 months ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆91Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆133Updated this week
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆70Updated 5 years ago
- ☆63Updated 6 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- ☆104Updated 4 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Library of approximate arithmetic circuits☆54Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆88Updated 6 months ago
- Automatic generation of FPGA-based learning accelerators for the neural network family☆63Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆78Updated 8 months ago