Alternatives and similar repositories for sv-parser

Users that are interested in sv-parser are comparing it to the libraries listed below

• dalance / svlint
  SystemVerilog linter
  ☆367Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆347Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆425Updated 2 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆334Updated last week
• dalance / svls
  SystemVerilog language server
  ☆543Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆428Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆671Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆237Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆539Updated 3 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆263Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆613Updated last week
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆145Updated 8 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆309Updated 4 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆875Updated last week
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆187Updated 7 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆463Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆217Updated 8 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆479Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆602Updated 7 months ago
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 9 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆185Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆481Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆278Updated last month
• svunit / svunit
  ☆208Updated 8 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆412Updated 10 months ago
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆438Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆721Updated 2 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆301Updated last month