Alternatives and similar repositories for sv-parser

Users that are interested in sv-parser are comparing it to the libraries listed below

• dalance / svlint
  SystemVerilog linter
  ☆361Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆344Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• dalance / svls
  SystemVerilog language server
  ☆542Updated 2 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆427Updated last month
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆329Updated 2 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆234Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆862Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆532Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆613Updated this week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆304Updated 3 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated 2 weeks ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆185Updated 6 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated last week
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆142Updated 8 months ago
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆468Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆461Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆296Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆716Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆409Updated 9 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 8 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆299Updated 2 weeks ago
• svunit / svunit
  ☆208Updated 7 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆232Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆593Updated 6 months ago