dalance / sv-parser

Related projects ⓘ

Alternatives and complementary repositories for sv-parser

• dalance / svlint
  SystemVerilog linter
  ☆315Updated 2 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆297Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆368Updated last week
• dalance / svls
  SystemVerilog language server
  ☆467Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆281Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆202Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆236Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆526Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆333Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆564Updated 3 weeks ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆251Updated 3 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆127Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆645Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆623Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆374Updated 4 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆243Updated 8 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆255Updated last week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆407Updated 2 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆167Updated 2 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆134Updated 3 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆371Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆361Updated last month
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆271Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆169Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆585Updated 2 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆195Updated last month
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆250Updated last month