SystemVerilog parser library fully compliant with IEEE 1800-2017
☆470Mar 30, 2026Updated last week
Alternatives and similar repositories for sv-parser
Users that are interested in sv-parser are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog linter☆379Nov 6, 2025Updated 5 months ago
- SystemVerilog language server☆569Apr 2, 2026Updated last week
- SystemVerilog compiler and language services☆1,002Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,807Mar 13, 2026Updated 3 weeks ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Test suite designed to check compliance with the SystemVerilog standard.☆371Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 4 years ago
- SystemVerilog to Verilog conversion☆713Mar 28, 2026Updated last week
- A SystemVerilog source file pickler.☆60Oct 20, 2024Updated last year
- A SystemVerilog Language Server☆195Nov 30, 2025Updated 4 months ago
- A hardware compiler based on LLHD and CIRCT☆267Jun 30, 2025Updated 9 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆321Jun 30, 2025Updated 9 months ago
- Code generation tool for control and status registers☆452Apr 2, 2026Updated last week
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A dependency management tool for hardware projects.☆360Apr 2, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆253Feb 22, 2026Updated last month
- Python bindings for slang, a library for compiling SystemVerilog☆66Jan 18, 2025Updated last year
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆782Jun 15, 2024Updated last year
- The UVM written in Python☆520Mar 30, 2026Updated last week
- An abstraction library for interfacing EDA tools☆757Apr 1, 2026Updated last week
- Hardware Description Languages☆1,140Updated this week
- Low Level Hardware Description — A foundation for building hardware design tools.☆432Apr 20, 2022Updated 3 years ago
- cocotb: Python-based chip (RTL) verification☆2,312Apr 2, 2026Updated last week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog grammar for tree-sitter☆113Nov 11, 2024Updated last year
- Verilator open-source SystemVerilog simulator and lint system☆3,517Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆657Apr 3, 2026Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆144Mar 25, 2026Updated 2 weeks ago
- Veryl: A Modern Hardware Description Language☆914Updated this week
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆499Mar 30, 2026Updated last week
- SystemVerilog synthesis tool☆231Mar 10, 2025Updated last year
- Yosys Open SYnthesis Suite☆4,385Updated this week
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,539Mar 31, 2026Updated last week
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆52Jan 13, 2021Updated 5 years ago
- Common SystemVerilog components☆727Mar 31, 2026Updated last week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,161Feb 21, 2026Updated last month
- Native Rust implementation of the FST waveform format from GTKWave.☆14Updated this week
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year