fukatani / awesome-hdl

Related projects ⓘ

Alternatives and complementary repositories for awesome-hdl

• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆140Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆134Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆84Updated 5 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆136Updated 3 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆48Updated 10 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆67Updated 4 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆76Updated 4 years ago
• slaclab / ruckus
  Vivado build system
  ☆71Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 10 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 6 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 9 months ago
• TM90 / awesome-hwd-tools
  A curated list of awesome open source hardware design tools
  ☆70Updated last week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆70Updated last month
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆69Updated this week
• idea-fasoc / fasoc
  ☆52Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆40Updated last week
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆78Updated 10 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆30Updated last month
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆84Updated 5 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆36Updated 5 years ago
• digital-design-hq / Digital-Resources
  ☆53Updated 3 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆52Updated last week
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆86Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆77Updated 2 weeks ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆69Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆202Updated this week