fukatani / awesome-hdlLinks
A curated list of awesome HDL, libraries, typical implementation and references.
☆37Updated 9 years ago
Alternatives and similar repositories for awesome-hdl
Users that are interested in awesome-hdl are comparing it to the libraries listed below
Sorting:
- A curated list of awesome resources for HDL design and verification☆163Updated last week
- OSVVM Documentation☆35Updated last month
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆218Updated last week
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆103Updated last year
- hardware library for hwt (= ipcore repo)☆43Updated last week
- Announcements related to Verilator☆41Updated 5 years ago
- FuseSoC standard core library☆147Updated 5 months ago
- Verilog/SystemVerilog Guide☆73Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- An open-source HDL register code generator fast enough to run in real time.☆74Updated last week
- ideas and eda software for vlsi design☆50Updated this week
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- FPGA tool performance profiling☆102Updated last year
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆95Updated 7 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- FPGA and Digital ASIC Build System☆78Updated 2 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- ☆61Updated 3 years ago
- Doxygen with verilog support☆39Updated 6 years ago
- A curated list of awesome open source hardware design tools☆84Updated 4 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 6 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆201Updated last year
- Streaming based VHDL parser.☆84Updated last year
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆68Updated last month
- Public repository for PySysC, (From SC Common Practices Subgroup)☆53Updated last year
- ☆99Updated 2 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆121Updated last week