Alternatives and similar repositories for rohd

Users that are interested in rohd are comparing it to the libraries listed below

• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆111Updated 2 weeks ago
• intel / rohd-vf
  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
  ☆46Updated 3 months ago
• intel / rohd-cosim
  Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
  ☆27Updated 7 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆324Updated 11 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆317Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆301Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆424Updated last year
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆246Updated 5 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆226Updated 3 weeks ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆300Updated 2 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆441Updated last month
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆377Updated 11 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated 3 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆439Updated 5 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆344Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆357Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 2 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆271Updated 3 weeks ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆483Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆316Updated last month
• dalance / svlint
  SystemVerilog linter
  ☆374Updated 3 months ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆445Updated 5 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆276Updated 3 weeks ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆229Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆282Updated last year
• phanrahan / magma
  magma circuits
  ☆264Updated last year
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆119Updated 8 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆462Updated 3 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year