intel / rohdLinks
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆446Updated this week
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below
Sorting:
- A hardware component library developed with ROHD.☆104Updated last week
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆45Updated 9 months ago
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆24Updated 3 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 4 months ago
- CORE-V Family of RISC-V Cores☆300Updated 7 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆353Updated 7 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆287Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated last month
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆294Updated last week
- FOSS Flow For FPGA☆407Updated 9 months ago
- A dependency management tool for hardware projects.☆324Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆416Updated last month
- VeeR EL2 Core☆297Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆325Updated 9 months ago
- ☆296Updated 2 weeks ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆274Updated 2 weeks ago
- ☆145Updated 2 years ago
- Communication framework for RTL simulation and emulation.☆301Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆268Updated 2 weeks ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆415Updated last week
- ☆92Updated last month
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated last week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated last week
- Ariane is a 6-stage RISC-V CPU☆146Updated 5 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆344Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆449Updated 7 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month