The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆484Jun 23, 2026Updated last week
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆47Oct 7, 2025Updated 8 months ago
- A hardware component library developed with ROHD.☆113May 3, 2026Updated last month
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆29May 20, 2026Updated last month
- high-performance RTL simulator☆194Jun 19, 2024Updated 2 years ago
- Hardware Description Languages☆1,158Apr 6, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463Jun 20, 2026Updated last week
- Circuit IR Compilers and Tools☆2,168Jun 24, 2026Updated last week
- SystemVerilog compiler and language services☆1,078Updated this week
- Hardware generator debugger☆78Feb 12, 2024Updated 2 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆610Jan 3, 2026Updated 5 months ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- An abstraction library for interfacing EDA tools☆771Jun 17, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,872Jun 22, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆259Updated this week
- The UVM written in Python☆556Updated this week
- Communication framework for RTL simulation and emulation.☆316Jun 22, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,426Jun 17, 2026Updated 2 weeks ago
- ☆21Updated this week
- A SystemVerilog Language Server☆205Nov 30, 2025Updated 7 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Jun 10, 2026Updated 3 weeks ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆459Apr 5, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆671Jun 16, 2026Updated 2 weeks ago
- Netlist API (and more) for EDA flow development☆143Updated this week
- A Linux-capable RISC-V multicore for and by the world☆812Jun 5, 2026Updated 3 weeks ago
- Raptor end-to-end FPGA Compiler and GUI☆98Dec 11, 2024Updated last year
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆109May 3, 2026Updated last month
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆160Jun 18, 2026Updated last week
- magma circuits☆263Oct 19, 2024Updated last year
- XLS: Accelerated HW Synthesis☆1,499Jun 23, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Code generation tool for control and status registers☆464May 30, 2026Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆379Jun 24, 2026Updated last week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆310Jun 19, 2026Updated last week
- A curated list of awesome resources for HDL design and verification☆174Updated this week
- Yosys Open SYnthesis Suite☆4,553Updated this week
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆34Oct 15, 2024Updated last year