The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆474Jan 18, 2026Updated 2 months ago
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆47Oct 7, 2025Updated 6 months ago
- A hardware component library developed with ROHD.☆112Mar 6, 2026Updated last month
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆29Jun 17, 2025Updated 9 months ago
- high-performance RTL simulator☆190Jun 19, 2024Updated last year
- Hardware Description Languages☆1,140Updated this week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A GPU acceleration flow for RTL simulation with batch stimulus☆120Apr 1, 2024Updated 2 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Updated this week
- Circuit IR Compilers and Tools☆2,080Updated this week
- SystemVerilog compiler and language services☆1,002Updated this week
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆597Jan 3, 2026Updated 3 months ago
- An abstraction library for interfacing EDA tools☆757Apr 1, 2026Updated last week
- A hardware compiler based on LLHD and CIRCT☆267Jun 30, 2025Updated 9 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,807Mar 13, 2026Updated 3 weeks ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆253Feb 22, 2026Updated last month
- The UVM written in Python☆520Mar 30, 2026Updated last week
- Communication framework for RTL simulation and emulation.☆311Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,407Feb 13, 2026Updated last month
- ☆21Mar 12, 2026Updated 3 weeks ago
- A SystemVerilog Language Server☆195Nov 30, 2025Updated 4 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆470Mar 30, 2026Updated last week
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- SystemVerilog synthesis tool☆232Mar 10, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆448Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆657Apr 3, 2026Updated last week
- Structural Netlist API (and more) for EDA post synthesis flow development☆135Apr 4, 2026Updated last week
- A Linux-capable RISC-V multicore for and by the world☆790Updated this week
- Raptor end-to-end FPGA Compiler and GUI☆96Dec 11, 2024Updated last year
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆94Mar 22, 2026Updated 2 weeks ago
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆156Apr 3, 2026Updated last week
- magma circuits☆265Oct 19, 2024Updated last year
- XLS: Accelerated HW Synthesis☆1,464Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Code generation tool for control and status registers☆452Apr 2, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆371Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆302Updated this week
- A curated list of awesome resources for HDL design and verification☆170Apr 3, 2026Updated last week
- Yosys Open SYnthesis Suite☆4,385Apr 3, 2026Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆264Sep 30, 2025Updated 6 months ago