Alternatives and similar repositories for rohd

Users that are interested in rohd are comparing it to the libraries listed below

• intel / rohd-hcl
  A hardware component library developed with ROHD.
  ☆107Updated last week
• intel / rohd-vf
  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
  ☆46Updated 2 months ago
• intel / rohd-cosim
  Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
  ☆26Updated 6 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆312Updated 10 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆369Updated 10 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆309Updated last week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆298Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆222Updated last month
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆415Updated 11 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆455Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆224Updated 10 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆206Updated 2 weeks ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆282Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆436Updated last week
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated 2 weeks ago
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆221Updated 9 months ago
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆335Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆269Updated last month
• stevehoover / warp-v
  WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
  ☆242Updated 7 months ago
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆306Updated 2 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated 2 weeks ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆298Updated last week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated last week
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆275Updated 3 months ago
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆118Updated 6 months ago