The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆489Aug 6, 2026Updated this week
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆48Jul 13, 2026Updated 3 weeks ago
- A hardware component library developed with ROHD.☆115Jul 1, 2026Updated last month
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆29May 20, 2026Updated 2 months ago
- Hardware Description Languages☆1,165Jul 9, 2026Updated last month
- high-performance RTL simulator☆195Aug 4, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A GPU acceleration flow for RTL simulation with batch stimulus☆123Apr 1, 2024Updated 2 years ago
- Circuit IR Compilers and Tools☆2,214Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆471Jul 28, 2026Updated 2 weeks ago
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- SystemVerilog compiler and language services☆1,108Updated this week
- A hardware compiler based on LLHD and CIRCT☆271Jun 30, 2025Updated last year
- An abstraction library for interfacing EDA tools☆786Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆618Jan 3, 2026Updated 7 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,907Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- The UVM written in Python☆564Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆266Jul 22, 2026Updated 3 weeks ago
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 3 weeks ago
- Communication framework for RTL simulation and emulation.☆316Aug 3, 2026Updated last week
- ☆22Aug 3, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,447Updated this week
- A SystemVerilog Language Server☆208Nov 30, 2025Updated 8 months ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Netlist API (and more) for EDA flow development☆157Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆463Jul 2, 2026Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆677Jul 7, 2026Updated last month
- Raptor end-to-end FPGA Compiler and GUI☆99Dec 11, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆825Jul 13, 2026Updated 3 weeks ago
- magma circuits☆265Oct 19, 2024Updated last year
- XLS: Accelerated HW Synthesis☆1,816Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- SystemVerilog (IEEE 1800-2017) Simulator☆71Updated this week
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆166Jul 29, 2026Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆291Sep 30, 2025Updated 10 months ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆385Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆314Jul 29, 2026Updated last week
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year