The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆487Jul 20, 2026Updated this week
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆48Jul 13, 2026Updated last week
- A hardware component library developed with ROHD.☆115Jul 1, 2026Updated 2 weeks ago
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆29May 20, 2026Updated 2 months ago
- Hardware Description Languages☆1,162Jul 9, 2026Updated last week
- high-performance RTL simulator☆194Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- Circuit IR Compilers and Tools☆2,201Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆467Updated this week
- Hardware generator debugger☆79Feb 12, 2024Updated 2 years ago
- SystemVerilog compiler and language services☆1,089Updated this week
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 2 weeks ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆613Jan 3, 2026Updated 6 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,894Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- The UVM written in Python☆560Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆260Updated this week
- RTLMeter benchmark suite☆31Jul 10, 2026Updated last week
- Communication framework for RTL simulation and emulation.☆314Updated this week
- ☆21Updated this week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,437Jul 2, 2026Updated 2 weeks ago
- A SystemVerilog Language Server☆205Nov 30, 2025Updated 7 months ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated 2 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Netlist API (and more) for EDA flow development☆149Updated this week
- Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework☆461Jul 2, 2026Updated 2 weeks ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆675Jul 7, 2026Updated 2 weeks ago
- Raptor end-to-end FPGA Compiler and GUI☆99Dec 11, 2024Updated last year
- A Linux-capable RISC-V multicore for and by the world☆823Jul 13, 2026Updated last week
- magma circuits☆264Oct 19, 2024Updated last year
- XLS: Accelerated HW Synthesis☆1,514Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SystemVerilog (IEEE 1800-2017) Simulator☆61Updated this week
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆166Jul 8, 2026Updated last week
- Open-source RTL logic simulator with CUDA acceleration☆287Sep 30, 2025Updated 9 months ago
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆380Updated this week
- Code generation tool for control and status registers☆462Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆311Jun 19, 2026Updated last month