intel / rohdLinks
The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
☆457Updated 2 weeks ago
Alternatives and similar repositories for rohd
Users that are interested in rohd are comparing it to the libraries listed below
Sorting:
- A hardware component library developed with ROHD.☆107Updated last month
- The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.☆46Updated 2 months ago
- Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators☆25Updated 5 months ago
- CORE-V Family of RISC-V Cores☆310Updated 10 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆369Updated 9 months ago
- FOSS Flow For FPGA☆415Updated 11 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆221Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆303Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆450Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 2 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- SystemVerilog linter☆370Updated last month
- A dependency management tool for hardware projects.☆337Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆298Updated last month
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆298Updated last week
- magma circuits☆263Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆205Updated this week
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆127Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆249Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆454Updated last month
- Qflow full end-to-end digital synthesis flow for ASIC designs☆221Updated last year
- Self checking RISC-V directed tests☆117Updated 6 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆288Updated 3 weeks ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆227Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆548Updated last month
- VeeR EL2 Core☆306Updated this week
- Communication framework for RTL simulation and emulation.☆304Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆332Updated last year