π A curated list of awesome RISC-V implementations
β143Mar 12, 2023Updated 3 years ago
Alternatives and similar repositories for awesome-riscv
Users that are interested in awesome-riscv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Description Languagesβ1,148Apr 6, 2026Updated last month
- A cheap iCE40 development board, designed on and for Raspberry Piβ29Jul 7, 2019Updated 6 years ago
- A simple script to build open-source FPGA tools.β54Oct 25, 2022Updated 3 years ago
- Atom Hardware IDEβ13May 4, 2021Updated 5 years ago
- PicoRVβ44Feb 19, 2020Updated 6 years ago
- Proton VPN Special Offer - Get 70% off β’ AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A curated list of awesome resources for HDL design and verificationβ174May 22, 2026Updated last week
- Using VexRiscv without installing Scalaβ39Nov 10, 2021Updated 4 years ago
- ZX80/81 implementation for the Ulx3sβ12May 4, 2022Updated 4 years ago
- Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and piβ¦β1,414May 20, 2026Updated last week
- 32-bit RISC-V system on chip for iCE40 FPGAsβ314May 25, 2023Updated 3 years ago
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- β37Sep 19, 2024Updated last year
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.β23Oct 24, 2023Updated 2 years ago
- KiCad bus length matching script.β30Jun 16, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)β259Aug 21, 2023Updated 2 years ago
- A configurable USB 2.0 device coreβ32Jun 12, 2020Updated 5 years ago
- Implementation of a cache memory in verilogβ15Dec 5, 2017Updated 8 years ago
- Basic RISC-V CPU implementation in VHDL.β176Sep 13, 2020Updated 5 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migenβ14Dec 6, 2019Updated 6 years ago
- An SDR for Raspberry Piβ35Jul 19, 2020Updated 5 years ago
- PicoRV32 - A Size-Optimized RISC-V CPUβ4,165Jun 27, 2024Updated last year
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.β245Mar 4, 2026Updated 2 months ago
- User-friendly explanation of Yosys optionsβ113Sep 25, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Siliceβ37Jul 2, 2023Updated 2 years ago
- nMigen examples for the ULX3S boardβ16Nov 30, 2020Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.β30Jun 13, 2022Updated 3 years ago
- β14May 24, 2025Updated last year
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.β467Sep 13, 2024Updated last year
- USB Full-Speed core written in migen/LiteXβ12Sep 19, 2019Updated 6 years ago
- Smol 2-stage RISC-V processor in nMigenβ26May 6, 2021Updated 5 years ago
- Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreakerβ104Feb 17, 2023Updated 3 years ago
- SERV - The SErial RISC-V CPUβ1,806Feb 19, 2026Updated 3 months ago
- Virtual machines for every use case on DigitalOcean β’ AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Multi-platform nightly builds of open source FPGA toolsβ303Nov 3, 2021Updated 4 years ago
- USB DFU bootloader gateware / firmware for FPGAsβ71Jan 30, 2026Updated 3 months ago
- β246Aug 12, 2022Updated 3 years ago
- Stack CPU Work In Progressβ29Jan 1, 2024Updated 2 years ago
- HDL symbol generatorβ203Feb 2, 2023Updated 3 years ago
- π₯οΈ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independeβ¦β2,071May 16, 2026Updated last week
- Tool to fix FT2232's uart interface configuration for ecp5evn (LFE5UM5G-85F-EVN) boardβ12Jun 17, 2021Updated 4 years ago