drom / awesome-riscv
😎 A curated list of awesome RISC-V implementations
☆125Updated last year
Related projects: ⓘ
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆126Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆187Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆208Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆107Updated last year
- Naive Educational RISC V processor☆69Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆213Updated last month
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆179Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆218Updated 9 months ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆223Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated last month
- FPGA tool performance profiling☆101Updated 6 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆79Updated 5 years ago
- CORE-V Family of RISC-V Cores☆199Updated 7 months ago
- SoC based on VexRiscv and ICE40 UP5K☆147Updated 5 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆133Updated 2 years ago
- Free collection of hardware modules written in Verilog for FPGAs and embedded systems.☆142Updated 3 weeks ago
- FuseSoC standard core library☆105Updated last month
- A curated list of awesome resources for HDL design and verification☆138Updated last week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆113Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆76Updated last month
- CoreScore☆135Updated last week
- FPGA Assembly (FASM) Parser and Generator☆88Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆93Updated 3 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- ☆76Updated 6 months ago
- VeeR EL2 Core☆243Updated this week
- Basic RISC-V CPU implementation in VHDL.☆158Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated 4 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆210Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆164Updated 8 months ago