drom / awesome-riscvLinks
😎 A curated list of awesome RISC-V implementations
☆137Updated 2 years ago
Alternatives and similar repositories for awesome-riscv
Users that are interested in awesome-riscv are comparing it to the libraries listed below
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆147Updated 9 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆241Updated 9 months ago
- CoreScore☆159Updated 6 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆218Updated 2 months ago
- FuseSoC standard core library☆146Updated 2 months ago
- Naive Educational RISC V processor☆85Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆221Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆292Updated this week
- Example LED blinking project for your FPGA dev board of choice☆179Updated 2 months ago
- FPGA Assembly (FASM) Parser and Generator☆95Updated 3 years ago
- FPGA tool performance profiling☆102Updated last year
- A 32-bit RISC-V soft processor☆312Updated 2 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆240Updated 2 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- Basic RISC-V CPU implementation in VHDL.☆168Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆184Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆265Updated 3 months ago
- RISC-V microcontroller IP core developed in Verilog☆176Updated 3 months ago
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- CORE-V Family of RISC-V Cores☆283Updated 5 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆402Updated this week
- A pipelined RISC-V processor☆57Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation