drom / awesome-riscv
😎 A curated list of awesome RISC-V implementations
☆135Updated 2 years ago
Alternatives and similar repositories for awesome-riscv:
Users that are interested in awesome-riscv are comparing it to the libraries listed below
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆235Updated 6 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆211Updated last month
- FuseSoC standard core library☆134Updated last month
- RISC-V microcontroller IP core developed in Verilog☆175Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆157Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆250Updated 2 weeks ago
- Naive Educational RISC V processor☆83Updated 6 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆174Updated last week
- A curated list of awesome resources for HDL design and verification☆146Updated this week
- CORE-V Family of RISC-V Cores☆265Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 5 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- FPGA tool performance profiling☆102Updated last year
- VeeR EL2 Core☆275Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆236Updated 2 months ago
- Experimental flows using nextpnr for Xilinx devices☆234Updated 7 months ago
- The multi-core cluster of a PULP system.☆91Updated last week
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- ☆283Updated 2 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated last month
- RISC-V Formal Verification Framework☆137Updated this week
- Generic Register Interface (contains various adapters)☆117Updated 7 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆116Updated 4 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆162Updated 3 months ago
- A 32-bit RISC-V soft processor☆313Updated 2 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 10 months ago